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? 2015 microchip technology inc. ds00001909a-page 1 highlights 2/3-port ethercat slave controller with 3 fieldbus memory management units (fmmus) and 4 syncmanagers interfaces to most 8/16-bit embedded controllers and 32-bit embedded controllers with an 8/16-bit bus integrated ethernet ph ys with hp auto-mdix wake on lan (wol) support low power mode allows systems to enter sleep mode until addressed by the master cable diagnostic support 1.8v to 3.3v variable voltage i/o integrated 1.2v regulator for single 3.3v operation low pin count and small body size package target applications motor motion control process/factory automation communication modules, interface cards sensors hydraulic & pneumatic valve systems operator interfaces key benefits integrated high-perform ance 100mbps ethernet transceivers - compliant with ieee 802.3/802.3u (fast ethernet) - 100base-fx support via exte rnal fiber transceiver - loop-back modes - automatic polarity detection and correction - hp auto-mdix ethercat slave controller - supports 3 fmmus - supports 4 syncmanagers - distributed clock support allo ws synchronization with other ethercat devices - 4k bytes of dpram 8/16-bit host bus interface - indexed register or multiplexed bus - allows local host to enter sleep mode until addressed by ethercat master - spi / quad spi support digital i/o mode for optimized system cost 3rd port for flexible network configurations comprehensive power management features - 3 power-down levels - wake on link status change (energy detect) - magic packet wakeup, wake on lan (wol), wake on broadcast, wake on perfect da - wakeup indicator event signal power and i/o - integrated power-on reset circuit - latch-up performance exceeds 150ma per eia/jesd78, class ii - jedec class 3a esd performance - single 3.3v power supply (integrated 1.2v regulator) additional features - multifunction gpios - ability to use low cost 25mhz crystal for reduced bom packaging - pb-free rohs compliant 64-pin qfn or 64-pin tqfp- ep available in commercial, industrial, and extended industrial* temp. ranges *extended temp. (105oc) is supported only in the 64-qfn with an external voltage regulator (internal regulator must be disabled) and 2.5v (typ) ethernet magnetics. lan9252 2/3-port ethercat? slave controller with integrated ethernet phys downloaded from: http:///
lan9252 ds00001909a-page 2 ? 2015 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the bes t documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this publication, please contact the marketing co mmunications department via e-mail at docerrors@microchip.com . we welcome your feedback. most current documentation to obtain the most up-to-date version of this document ation, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data s heet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the version number, (e.g., ds30000000a is version a of document ds30000000). errata an errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur- rent devices. as device/doc umentation issues become known to us, we will publish an errata s heet. the errata will specify the revision of silicon and revision of document to which it applies. to determine if an errata sheet exis ts for a particular device, please check with one of the following: microchips worldwide web site; http://www.microchip.com your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include -literature number) yo u are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products. downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 3 lan9252 1.0 preface ................................................................................................................... ......................................................................... 4 2.0 general description ........................................................................................................................................................................ 8 3.0 pin descriptions and configuration ........................................................................................ ....................................................... 11 4.0 power connections ......................................................................................................... .............................................................. 29 5.0 register map ................................................................................................................................................................................. 32 6.0 clocks, resets, and power management ...................................................................................... ............................................... 37 7.0 configuration straps ...................................................................................................... ............................................................... 51 8.0 system interrupts ......................................................................................................... ................................................................. 53 9.0 host bus interface ........................................................................................................................................................................ 62 10.0 spi/sqi slave ............................................................................................................ ............................................................... 102 11.0 ethernet phys ............................................................................................................ .............................................................. 120 12.0 ethercat .................................................................................................................................................................................. 196 13.0 eeprom interface ................................................................................................................................................................... 295 14.0 chip mode configuration .......................................................................................................................................................... 296 15.0 general purpose timer & free-running clock ............................................................................... ......................................... 297 16.0 miscellaneous ........................................................................................................................................................................... 301 17.0 jtag ......................................................................................................................................................................................... 305 18.0 operational charac teristics .............................................................................................. ......................................................... 307 19.0 package outlines ......................................................................................................... ............................................................. 322 20.0 revision history ........................................................................................................................................................................ 325 downloaded from: http:///
lan9252 ds00001909a-page 4 ? 2015 microchip technology inc. 1.0 preface 1.1 general terms table 1-1: general terms term description 10base-t 10 mbps ethernet, ieee 802.3 compliant 100base-tx 100 mbps fast ethernet, ieee802.3u compliant adc analog-to-digital converter alr address logic resolution an auto-negotiation blw baseline wander bm buffer manager - part of the switch fabric bpdu bridge protocol data unit - messages which carry the spanning tree protocol informa- tion byte 8 bits csma/cd carrier sense multiple access/collision detect csr control and status registers ctr counter da destination address dword 32 bits epc eeprom controller fcs frame check sequence - the extra checksum characters added to the end of an ethernet frame, used for error detection and correction. fifo first in first out buffer fsm finite state machine gpio general purpose i/o host external system (includes proce ssor, application software, etc.) igmp internet group management protocol inbound refers to data input to the device from the host level-triggered sticky bit this type of status bit is set whenever the c ondition that it represents is asserted. the bit remains set until the condition is no longer true and the status bit is cleared by writ- ing a zero. lsb least significant bit lsb least significant byte lvds low voltage differential signaling mdi medium dependent interface mdix media independent interf ace with crossover mii media independent interface miim media independent interface management mil mac interface layer mld multicast listening discovery mlt-3 multi-level transmission encoding (3-levels). a tri-level encoding method where a change in the logic level represents a code bi t 1 and the logic output remaining at the same level represent s a code bit 0. msb most significant bit msb most significant byte downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 5 lan9252 nrzi non return to zero inverted. this encoding method inverts the signal for a 1 and leaves the signal unchanged for a 0 n/a not applicable nc no connect oui organizationally unique identifier outbound refers to data output fr om the device to the host piso parallel in serial out pll phase locked loop ptp precision time protocol reserved refers to a reserved bit field or address. unless otherwise noted, reserved bits must always be zero for write operations. unle ss otherwise noted, va lues are not guaran- teed when reading reserved bits. unless other wise noted, do not read or write to reserved addresses. rtc real-time clock sa source address sfd start of frame delimiter - the 8-bit value indicating the end of the preamble of an ethernet frame. sipo serial in parallel out smi serial management interface sqe signal quality error (also known as heartbeat) ssd start of stream delimiter udp user datagram protocol - a connectionl ess protocol run on top of ip networks uuid universally unique identifier word 16 bits table 1-1: general terms (continued) term description downloaded from: http:///
lan9252 ds00001909a-page 6 ? 2015 microchip technology inc. 1.2 buffer types table 1-2: buffer types buffer type description is schmitt-triggered input vis variable voltage schmitt-triggered input vo8 variable voltage output with 8 ma sink and 8 ma source vod8 variable voltage open-drain output with 8 ma sink vo12 variable voltage output with 12 ma sink and 12 ma source vod12 variable voltage open-drain output with 12 ma sink vos12 variable voltage open-sour ce output with 12 ma source vo16 variable voltage output with 16 ma sink and 16 ma source pu 50 a (typical) internal pull-up. unless other wise noted in the pin description, internal pull- ups are always enabled. internal pull-up resistors prevent unconnected inputs from floating. do not rely on in ternal resistors to drive signals external to the device. when connected to a load that must be pulled high, an external resistor must be added. pd 50 a (typical) internal pull-down. unless ot herwise noted in the pin description, internal pull-downs are always enabled. internal pull-down resistors prevent unconnected inputs from floating. do not rely on internal resistors to drive signals external to the device. when connected to a load that must be pulled low, an external resistor must be added. ai analog input aio analog bidirectional iclk crystal oscillator input pin oclk crystal oscillator output pin ilvpecl low voltage pecl input pin olvpecl low voltage pecl output pin p power pin downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 7 lan9252 1.3 register nomenclature table 1-3: register nomenclature register bit type notation register bit description r read: a register or bit with this attribute can be read. w read: a register or bit with this attribute can be written. ro read only: read only. writes have no effect. wo write only: if a register or bit is write-on ly, reads will return unspecified data. wc write one to clear: writing a one clears the value. writing a zero has no effect wac write anything to clear: writing anything clears the value. rc read to clear: contents is cleared after the read. writes have no effect. ll latch low: clear on read of register. lh latch high: clear on read of register. sc self-clearing: contents are self-cleared after the being set. writes of zero have no effect. contents can be read. ss self-setting: contents are self-setting after bei ng cleared. writes of one have no effect. contents can be read. ro/lh read only, latch high: bits with this attribute will stay high until the bit is read. after it is read, the bit will either remain high if th e high condition remains, or will go low if the high condition has been removed. if the bit has not been read, the bit will remain high regardless of a change to the high condition. this mode is used in some ethernet phy registers. nasr not affected by software reset. the state of nasr bits do not change on assertion of a software reset. reserved reserved field: reserved fields must be written with zeros to ensure future compati- bility. the value of reserved bits is not guaranteed on a read. downloaded from: http:///
lan9252 ds00001909a-page 8 ? 2015 microchip technology inc. 2.0 general description the lan9252 is a 2/3-port ethercat slave controller wi th dual integrated ethernet phys which each contain a full- duplex 100base-tx transceiver and support 100mbps (100 base-tx) operation. the lan9252 supports hp auto- mdix, allowing the use of direct connect or cross-over lan cables. 100base-fx is supported via an external fiber transceiver. the lan9252 includes an ethercat slave controller with 4k bytes of dual port memory (dpram) and 3 fieldbus mem- ory management units (fmmus). each f mmu performs the task of mapping logical addresses to physical addresses. the ethercat slave controller also incl udes 4 syncmanagers to allow the exc hange of data between the ethercat mas- ter and the local application. each syncmanager's directio n and mode of operation is configured by the ethercat mas- ter. two modes of operation are avail able: buffered mode or mailbox mode. in the buffered mode, both the local microcontroller and ethercat master ca n write to the device concurrently. the buffer within the lan9252 will always contain the latest data. if newer data arrives before the old data can be read out, the old data will be dropped. in mailbox mode, access to the buffer by the local microcontroller and the ethercat master is pe rformed using handshakes, guar- anteeing that no data will be dropped. two user selectable host bus interface options are available: indexed register access this implementation provides three index/data regist er banks, each with independent byte/word to dword conversion. internal registers are access ed by first writing one of the three index registers, followed by reading or writing the corresponding data regist er. three index/data register banks support up to 3 independent driver threads without access conflicts. each thread can write its assigned index register without the issue of another thread overwriting it. two 16-bit cycles or four 8-bit cycles are required within the same 32-bit index/data register - however, these access can be interleav ed. direct (non-indexed) read and write accesses are supported to the process data fifos. the direct fifo access provides independent byte/word to dword conversion, support- ing interleaved accesses with the index/data registers. multiplexed address/data bus this implementation provides a multip lexed address and data bus with both single phase and dual phase address support. the address is loaded with an address strobe fo llowed by data access using a read or write strobe. two back to back 16-bit data cycles or 4 back to back 8-bit data cycles are required within the same 32-bit dword. these accesses must be sequential without any interleaved accesses to other regist ers. burst read and write accesses are supported to t he process data fifos by per forming one address cycle followed by multiple read or write data cycles. the hbi supports 8/16-bit operation with big, little, and mixed endian operations. two process data ram fifos inter- face the hbi to the ethercat slave controller and facilitat e the transferring of process data information between the host cpu and the ethercat slave. a configurable host interrupt pi n allows the device to inform the host cpu of any internal interrupts. an spi / quad spi slave controller provides a low pin count synchronous slave interface that facilitates communication between the device and a host system. the spi / quad spi slave allows access to the system csrs, internal fifos and memories. it supports single and multiple register read and write commands with in crementing, decrementing and static addressing. single, dual and quad bit lanes are supported with a clock rate of up to 80 mhz. the lan9252 supports numerous power management and wakeup features. the lan9252 can be placed in a reduced power mode and can be programmed to issue an external wake signal (irq) via several methods, including magic packet, wake on lan, wake on broadcast, wake on perfect da, and link status change. this signal is ideal for triggering system power-up using remote ethernet wakeup even ts. the device can be removed from the low power state via a host processor command or one of the wake events. for simple digital modules without microcontrollers, the lan9252 can also operate in digital i/o mode where 16 digital signals can be controlled or moni tored by the ethercat master. to enable star or tree network topologies , the device can be configured as a 3- port slave, providing an additional mii port. this port can be connected to an external phy, formi ng a tap along the current daisy chain, or to another lan9252 creating a 4-port solution. the mii port can point upstream (as port 0) or downstream (as port 2). led support consists of a standard run indicator and a link / activity indicator per port. a 64-bit distributed clock is included to enable high-precision synchronization and to provide accurate information about the local timing of data acquisition. the lan9252 can be configured to operate via a single 3.3v supply utilizing an integrated 3. 3v to 1.2v linear regulator. the linear regulator may be optionally disabled, allowing usa ge of a high efficiency external regulator for lower system power dissipation. downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 9 lan9252 the lan9252 is available in commercial, industrial, and extended industrial temperature ranges. figure 2-1 details a typical system app lication, while figure 2-2 provides an internal block diagram of the lan9252. the lan9252 can operate in microcontroller, expansion, or digital i/o mode: figure 2-1: system block diagram figure 2-2: internal block diagram lan9252 microprocessor/ microcontroller local bus eeprom magnetics rj45 25mhz magnetics rj45 ethercat slave ethercat master ethercat slave ethercat slave phy rj45 ethercat slave 100 phy w/ fiber registers ethercat slave controller syncmanager fmmu esc address space registers / ram loopback port 0 auto fowarder loopback port 2 auto fowarder led controller to optional leds system interrupt controller irq system clocks/ reset controller external 25mhz crystal i 2 c eeprom 100 phy w/ fiber registers lan9252 ethernet ethernet parallel data interface to 8/16-bit host bus, mii, spi, digital ios, gpios to i 2 c loopback port 1 auto fowarder mii downloaded from: http:///
lan9252 ds00001909a-page 10 ? 2015 microchip technology inc. microcontroller mode: the lan9252 communicates with the microcont roller through an sram-like slave interface. the simple, yet highly functional host bus interface provides a glue-less conn ection to most common 8 or 16-bit micro- processors and microcontrollers as well as 32-b it microprocessors with an 8 or 16-bit external bus. alternatively, the device can be accessed via spi or quad spi, while also providing up to 16 inputs or outputs for general purpose usage. expansion mode: while the device is in spi or quad spi mode, a third networking port can be enabled to provide an additional mii port. this port can be connected to an exter nal phy, to enable star or tree network topologies, or to another lan9252 to create a four port solution. this port ca n be configured for the upst ream or downstream direction. digital i/o mode: for simple digital modules without microcontrolle rs, the lan9252 can operate in digital i/o mode where 16 digital signals can be controlled or monitored by the ethercat master. six control signals are also provided. figure 2-3 provides a system level overview of each mode of operation. figure 2-3: modes of operation lan9252 microprocessor/ microcontroller spi / quad spi lan9252 microprocessor/ microcontroller host bus interface magnetics or fiber xcvr rj45 or fiber magnetics or fiber xcvr rj45 or fiber magnetics or fiber xcvr rj45 or fiber magnetics or fiber xcvr rj45 or fiber microcontroller mode (via host bus interface) microcontroller mode (via spi) digital i/os lan9252 phy m i i lan9252 magnetics or fiber xcvr rj45 or fiber magnetics or fiber xcvr rj45 or fiber magnetics or fiber xcvr rj45 or fiber magnetics or fiber xcvr rj45 or fiber magnetics or fiber xcvr digital i/o mode expansion mode gpios microprocessor/ microcontroller spi / quad spi rj45 or fiber downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 11 lan9252 3.0 pin descriptions and configuration 3.1 64-qfn pin assignments figure 3-1: 64-qfn pin assignments (top view) note: when a # is used at the end of the signal name, it indica tes that the signal is active low. for example, rst# indicates that the reset signal is active low. the buffer type for each signal is indicated in the b uffer type column of the pin description tables in sec- tion 3.3, "pin descriptions" . a description of the buffer types is provided in section 1.2, "buffer types" . note: exposed pad (vss ) on bottom of package must be connected to ground with a via field. (connect exposed pad to ground with a via field) vss lan9252 64-qfn (top view) 56 7 8 9 1011 12 2122 23 24 25 26 27 28 4443 42 41 40 39 38 37 6059 58 57 56 55 54 53 fxlosen reg_en fxsda/fxlosa/fxsdena fxsdb/fxlosb/fxsdenb rst# d2/ad2/sof/sio2 d1/ad1/eof/so/sio1 vddio linkactled1/tdi/chip_mode1 runled/e2psize eescl/tck vddcr d6/ad6/digio0/gpi0/gpo0/mii_rxclk d3/ad3/wd_trig/sio3 rbias vdd12tx1 vdd33txrx1 vdd33bias rxpa cs/digio13/gpi13/gpo13/mii_rxd1 a1/alelo/oe_ext/mii_clk25 d11/ad11/digio5/gpi5/gpo5/mii_txd0 d12/ad12/digio6/gpi6/gpo6/mii_txd1 vddio d9/ad9/latch_in/sck txna eesda/tms txpa a2/alehi/digio10/gpi10/gpo10/ linkactled2/mii_linkpol rxna vddcr irq 5251 6261 34 1314 1920 2930 3635 4645 d10/ad10/digio4/gpi4/gpo4/mii_txen a3/digio11/gpi11/gpo11/mii_rxdv a4/digio12/gpi12/gpo12/mii_rxd0 wr/enb/digio14/gpi14/gpo14/mii_rxd2 vddcr vdd33 oscvss oscvdd12 vdd12tx2 rxpb rxnb txpb testmode d8/ad8/digio2/gpi2/gpo2/mii_mdio d7/ad7/digio1/gpi1/gpo1/mii_mdc vddio 12 osco osci 16 15 d13/ad13/digio7/gpi7/gpo7/mii_txd2/tx_shift0 d14/ad14/digio8/gpi8/gpo8/mii_txd3/tx_shift1 1718 d0/ad0/wd_state/si/sio0 sync1/latch1 32 vddio rd/rd_wr/digio15/gpi15/gpo15/mii_rxd3 31 3433 a0/d15/ad15/digio9/gpi9/gpo9/mii_rxer sync0/latch0 48 vddio 47 linkactled0/tdo/chip_mode0 5049 d5/ad5/outvalid/scs# d4/ad4/digio3/gpi3/gpo3/mii_link 64 txnb vdd33txrx2 63 downloaded from: http:///
lan9252 ds00001909a-page 12 ? 2015 microchip technology inc. table 3-1 details the 64-qfn package pin assignments in table format. as shown, select pin functions may change based on the devices mode of operati on. for modes where a specific pin has no function, the table cell will be marked with -. table 3-1: 64-qfn package pin assignments pin number hbi indexed mode pin name hbi multiplexed mode pin name digital i/o mode pin name spi with gpio mode pin name spi with mii mode pin name 1 osci 2 osco 3 oscvdd12 4 oscvss 5 vdd33 6 vddcr 7 reg_en 8 fxlosen 9 fxsda/fxlosa/fxsdena 10 fxsdb/fxlosb/fxsdenb 11 rst# 12 d2 ad2 sof sio2 13 d1 ad1 eof so/sio1 14 vddio 15 d14 ad14 digio8 gpi8/gpo8 mii_txd3/ tx_shift1 16 d13 ad13 digio7 gpi7/gpo7 mii_txd2/ tx_shift0 17 d0 ad0 wd_state si/sio0 18 sync1/latch1 19 d9 ad9 latch_in sck 20 vddio 21 d12 ad12 digio6 gpi6/gpo6 mii_txd1 22 d11 ad11 digio5 gpi5/gpo5 mii_txd0 23 d10 ad10 digio4 gpi4/gpo4 mii_txen 24 vddcr 25 a1 alelo oe_ext - mii_clk25 26 a3 - digio11 gpi11/gpo11 mii_rxdv 27 a4 - digio12 gpi12/gpo12 mii_rxd0 28 cs digio13 gpi13/gpo13 mii_rxd1 29 a2 alehi digio10 gpi 10/gpo10 linkactled2/ mii_linkpol 30 wr/enb digio14 gpi14/gpo14 mii_rxd2 downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 13 lan9252 31 rd/rd_wr digio15 gpi15/gpo15 mii_rxd3 32 vddio 33 a0/d15 ad15 digio9 gpi9/gpo9 mii_rxer 34 sync0/latch0 35 d3 ad3 wd_trig sio3 36 d6 ad6 digio0 gpi0/gpo0 mii_rxclk 37 vddio 38 vddcr 39 d7 ad7 digio1 gpi1/gpo1 mii_mdc 40 d8 ad8 digio2 gpi2/gpo2 mii_mdio 41 testmode 42 eesda/tms 43 eescl/tck 44 irq 45 runled/e2psize 46 linkactled1/tdi/chip_mode1 47 vddio 48 linkactled0/tdo/chip_mode0 49 d4 ad4 digio3 gpi3/gpo3 mii_link 50 d5 ad5 outvalid scs# 51 vdd33txrx1 52 txna 53 txpa 54 rxna 55 rxpa 56 vdd12tx1 57 rbias 58 vdd33bias 59 vdd12tx2 60 rxpb 61 rxnb 62 txpb 63 txnb 64 vdd33txrx2 exposed pad vss table 3-1: 64-qfn package pi n assignments (continued) pin number hbi indexed mode pin name hbi multiplexed mode pin name digital i/o mode pin name spi with gpio mode pin name spi with mii mode pin name downloaded from: http:///
lan9252 ds00001909a-page 14 ? 2015 microchip technology inc. 3.2 64-tqfp-ep pin assignments . figure 3-2: 64-tqfp-ep pin assignments (top view) note: when an # is used at the end of the sig nal name, it indicates that the signal is active low. for example, rst# indicates that the reset signal is active low. the buffer type for each signal is indicated in the b uffer type column of the pin description tables in sec- tion 3.3, "pin descriptions" . a description of the buffer types is provided in section 1.2, "buffer types" . note: exposed pad (vss ) on bottom of package must be connected to ground with a via field. (connect exposed pad to ground with a via field) vss lan9252 64-tqfp-ep (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 fxlosen reg_en fxsda/fxlosa/fxsdena fxsdb/fxlosb/fxsdenb rst# d2/ad2/sof/sio2 d1/ad1/eof/so/sio1 vddio vddcr vdd33 oscvss oscvdd12 osco osci d13/ad13/digio7/gpi7/gpo7/mii_txd2/tx_shift0 d14/ad14/digio8/gpi8/gpo8/mii_txd3/tx_shift1 cs/digio13/gpi13/gpo13/mii_rxd1 a1/alelo/oe_ext/mii_clk25 d11/ad11/digio5/gpi5/gpo5/mii_txd0 d12/ad12/digio6/gpi6/gpo6/mii_txd1 vddio d9/ad9/latch_in/sck a2/alehi/digio10/gpi10/gpo10/ linkactled2/mii_linkpol vddcr d10/ad10/digio4/gpi4/gpo4/mii_txen a3/digio11/gpi11/gpo11/mii_rxdv a4/digio12/gpi12/gpo12/mii_rxd0 wr/enb/digio14/gpi14/gpo14/mii_rxd2 d0/ad0/wd_state/si/sio0 sync1/latch1 vddio rd/rd_wr/digio15/gpi15/gpo15/mii_rxd3 linkactled1/tdi/chip_mode1 runled/e2psize eescl/tck vddcr d6/ad6/digio0/gpi0/gpo0/mii_rxclk d3/ad3/wd_trig/sio3 eesda/tms irq testmode d8/ad8/digio2/gpi2/gpo2/mii_mdio d7/ad7/digio1/gpi1/gpo1/mii_mdc vddio a0/d15/ad15/digio9/gpi9/gpo9/mii_rxer sync0/latch0 vddio linkactled0/tdo/chip_mode0 rbias vdd12tx1 vdd33txrx1 vdd33bias rxpa txna txpa rxna vdd12tx2 rxpb rxnb txpb d5/ad5/outvalid/scs# d4/ad4/digio3/gpi3/gpo3/mii_link txnb vdd33txrx2 downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 15 lan9252 table 3-2 details the 64-tqfp-ep package pin assignments in table format. as shown, select pin functions may change based on the devices mode of operati on. for modes where a specific pin has no function, the table cell will be marked with -. table 3-2: 64-tqfp-ep package pin assignments pin number hbi indexed mode pin name hbi multiplexed mode pin name digital i/o mode pin name spi with gpio mode pin name spi with mii mode pin name 1 osci 2 osco 3 oscvdd12 4 oscvss 5 vdd33 6 vddcr 7 reg_en 8 fxlosen 9 fxsda/fxlosa/fxsdena 10 fxsdb/fxlosb/fxsdenb 11 rst# 12 d2 ad2 sof sio2 13 d1 ad1 eof so/sio1 14 vddio 15 d14 ad14 digio8 gpi8/gpo8 mii_txd3/ tx_shift1 16 d13 ad13 digio7 gpi7/gpo7 mii_txd2/ tx_shift0 17 d0 ad0 wd_state si/sio0 18 sync1/latch1 19 d9 ad9 latch_in sck 20 vddio 21 d12 ad12 digio6 gpi6/gpo6 mii_txd1 22 d11 ad11 digio5 gpi5/gpo5 mii_txd0 23 d10 ad10 digio4 gpi4/gpo4 mii_txen 24 vddcr 25 a1 alelo oe_ext - mii_clk25 26 a3 - digio11 gpi11/gpo11 mii_rxdv 27 a4 - digio12 gpi12/gpo12 mii_rxd0 28 cs digio13 gpi13/gpo13 mii_rxd1 29 a2 alehi digio10 gpi 10/gpo10 linkactled2/ mii_linkpol 30 wr/enb digio14 gpi14/gpo14 mii_rxd2 downloaded from: http:///
lan9252 ds00001909a-page 16 ? 2015 microchip technology inc. 31 rd/rd_wr digio15 gpi15/gpo15 mii_rxd3 32 vddio 33 a0/d15 ad15 digio9 gpi9/gpo9 mii_rxer 34 sync0/latch0 35 d3 ad3 wd_trig sio3 36 d6 ad6 digio0 gpi0/gpo0 mii_rxclk 37 vddio 38 vddcr 39 d7 ad7 digio1 gpi1/gpo1 mii_mdc 40 d8 ad8 digio2 gpi2/gpo2 mii_mdio 41 testmode 42 eesda/tms 43 eescl/tck 44 irq 45 runled/e2psize 46 linkactled1/tdi/chip_mode1 47 vddio 48 linkactled0/tdo/chip_mode0 49 d4 ad4 digio3 gpi3/gpo3 mii_link 50 d5 ad5 outvalid scs# 51 vdd33txrx1 52 txna 53 txpa 54 rxna 55 rxpa 56 vdd12tx1 57 rbias 58 vdd33bias 59 vdd12tx2 60 rxpb 61 rxnb 62 txpb 63 txnb 64 vdd33txrx2 exposed pad vss table 3-2: 64-tqfp-ep package pin assignments (continued) pin number hbi indexed mode pin name hbi multiplexed mode pin name digital i/o mode pin name spi with gpio mode pin name spi with mii mode pin name downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 17 lan9252 3.3 pin descriptions this section contains descriptions of the various lan9252 pins. the pin descriptions have been broken into functional groups as follows: lan port a pin descriptions lan port b pin descriptions lan port a & b power and common pin descriptions ethercat mii port & configuration strap pin descriptions host bus pin descriptions spi/sqi pin descriptions ethercat distributed clock pin descriptions ethercat digital i/o and gpio pin descriptions eeprom pin descriptions led & configuration strap pin descriptions miscellaneous pin descriptions jtag pin descriptions core and i/o power pin descriptions table 3-3: lan port a pin descriptions num pins name symbol buffer type description 1 port a tp tx/rx positive channel 1 txpa aio port a twisted pair tran smit/receive positive channel 1. see note 1 port a fx tx positive olvpecl port a fiber tran smit positive. 1 port a tp tx/rx negative channel 1 txna aio port a twisted pair transmit/receive negative channel 1. see note 1 . port a fx tx negative olvpecl port a fiber transmit negative. 1 port a tp tx/rx positive channel 2 rxpa aio port a twisted pair tran smit/receive positive channel 2. see note 1 . port a fx rx positive ai port a fiber receive positive. 1 port a tp tx/rx negative channel 2 rxna aio port a twisted pair transmit/receive negative channel 2. see note 1 . port a fx rx negative ai port a fiber receive negative. downloaded from: http:///
lan9252 ds00001909a-page 18 ? 2015 microchip technology inc. note 1: in copper mode, either channel 1 or 2 may function as the transmit pair while the other channel functions as the receive pair. the pin name symbols for the twisted pair pins apply to a normal connection. if hp auto- mdix is enabled and a reverse connection is detected or manually selected, the rx and tx pins will be swapped internally. note 2: configuration strap pins are ident ified by an underlined symbol name. configuration strap values are latched on power-on reset or rst# de-assertion. refer to section 7.0, "configuration straps," on page 51 for more in formation. 1 port a fx signal detect (sd) fxsda ilvpecl port a fiber signal detect. when fx-los mode is not selected, this pin functi ons as the signal detect input from the external transceiver. a level above 2 v (typ.) indicates valid signal. when fx-los mode is selected, the input buffer is disabled. port a fx loss of signal (los) fxlosa is (pu) port a fiber loss of signal. when fx-los mode is selected (via fx_los_strap_1 ), this pin functions as the loss of signal input from the external trans- ceiver. a high indicates los while a low indicates valid signal. when fx-los mode is not selected, the input buffer and pull-up are disabled. port a fx-sd enable strap fxsdena ai port a fx-sd enable. when fx-los mode is not selected, this strap input selects between fx-sd and copper twisted pair mode. a level above 1 v (typ.) selects fx-sd. when fx-los mode is selected, the input buffer is disabled. see note 2 . note: port a is connected to the ethercat port 0 or 2. table 3-4: lan port b pin descriptions num pins name symbol buffer type description 1 port b tp tx/rx positive channel 1 txpb aio port b twisted pair tran smit/receive positive channel 1. see note 3 port b fx tx positive olvpecl port b fiber tran smit positive. 1 port b tp tx/rx negative channel 1 txnb aio port b twisted pair transmit/receive negative channel 1. see note 3 . port b fx tx negative olvpecl port b fiber transmit negative. table 3-3: lan port a pin descriptions (continued) num pins name symbol buffer type description downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 19 lan9252 note 3: in copper mode, either channel 1 or 2 may function as the transmit pair while the other channel functions as the receive pair. the pin name symbols for the twisted pair pins apply to a normal connection. if hp auto- mdix is enabled and a reverse connection is detected or manually selected, the rx and tx pins will be swapped internally. note 4: configuration strap pins are ident ified by an underlined symbol name . configuration strap values are latched on power-on reset or rst# de-assertion. refer to section 7.0, "configuration straps," on page 51 for more in formation. 1 port btp tx/rx positive channel 2 rxpb aio port b twisted pair tran smit/receive positive channel 2. see note 3 . port b fx rx positive ai port b fiber receive positive. 1 port b tp tx/rx negative channel 2 rxnb aio port b twisted pair transmit/receive negative channel 2. see note 3 . port b fx rx negative ai port b fiber receive negative. 1 port b fx signal detect (sd) fxsdb ilvpecl port b fiber signal detect. when fx-los mode is not selected, this pin functi ons as the signal detect input from the external transceiver. a level above 2 v (typ.) indicates valid signal. when fx-los mode is selected, the input buffer is disabled. port b fx loss of signal (los) fxlosb is (pu) port b fiber loss of signal. when fx-los mode is selected (via fx_los_strap_2 ), this pin functions as the loss of signal input from the external trans- ceiver. a high indicates los while a low indicates valid signal. when fx-los mode is not selected, the input buffer and pull-up are disabled. port b fx-sd enable strap fxsdenb ai port b fx-sd enable. when fx-los mode is not selected, this strap input selects between fx-sd and copper twisted pair mode. a level above 1 v (typ.) selects fx-sd. when fx-los mode is selected, the input buffer is disabled. see note 4 . note: port b is connected to ethercat port 1. table 3-4: lan port b pin descriptions (continued) num pins name symbol buffer type description downloaded from: http:///
lan9252 ds00001909a-page 20 ? 2015 microchip technology inc. note 5: refer to section 4.0, "power connections," on page 29 , the device reference schematics, and the device lancheck schematic checklist for additional connection information. table 3-5: lan port a & b power and common pin descriptions num pins name symbol buffer type description 1 bias reference rbias ai used for internal bias circuits. connect to an exter- nal 12.1 k ? , 1% resistor to ground. refer to the device reference schematic for connec- tion information. note: the nominal voltage is 1.2 v and the resistor will dissipate approximately 1 mw of power. 1 port a and b fx-los enable strap fxlosen ai port a and b fx-los enable. this 3 level strap input selects between fx-los and fx-sd / copper twisted pair mode. a level below 1 v (typ.) selects fx-sd / copper twisted pair for ports a and b, further determined by fxsdena and fxsdenb . a level of 1.5 v selects fx-los for port a and fx- sd / copper twisted pair for port b, further deter- mined by fxsdenb . a level above 2 v (typ.) selects fx-los for ports a and b. 1 +3.3 v port a analog power supply vdd33txrx1 p see note 5 . 1 +3.3 v port b analog power supply vdd33txrx2 p see note 5 . 1 +3.3 v master bias power supply vdd33bias p see note 5 . 1 port a transmitter +1.2 v power supply vdd12tx1 p this pin is supplied from either an external 1.2 v supply or from the devices internal regulator via the pcb. this pin must be tied to the vdd12tx2 pin for proper operation. see note 5 . 1 port b transmitter +1.2 v power supply vdd12tx2 p this pin is supplied from either an external 1.2 v supply or from the devices internal regulator via the pcb. this pin must be tied to the vdd12tx1 pin for proper operation. see note 5 . downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 21 lan9252 note 6: a series terminating resistor is recommended for the best pcb signal integrity. note 7: an external supplemental pull-up may be needed, d epending upon the input current loading of the external mac/phy device. note 8: configuration strap pins are ident ified by an underlined symbol name . configuration strap values are latched on power-on reset or rst# de-assertion. refer to section 7.0, "configuration straps," on page 51 for more in formation. table 3-6: ethercat mii port & co nfiguration strap pin descriptions num pins name symbol buffer type description 1 25 mhz clock mii_clk25 vo12 note 6 this pin is a free-running 25 mhz clock that can be used as the clock input to the phy. 4 receive data mii port mii_rxd[3:0] vis (pd) these pins are the receive data from the external phy. 1 receive data valid mii port mii_rxdv vis (pd) this pin is the receive data valid signal from the external phy. 1 receive error mii port mii_rxer vis (pd) this pin is the receive error signal from the external phy. 1 receive clock mii port mii_rxclk vis (pd) this pin is the receive clock from the external phy. 4 transmit data mii port mii_txd[3:0] vo8 these pins are the transmit data to the external phy. mii transmit timing shift configuration strap tx_shift[1:0] vis (pu) note 7 these straps configure the value of the external mii bus tx timing shift hard-strap. see note 8 . tx_shift[1] is on mii_txd[3] and tx_shift[0] is on mii_txd[2] . 1 transmit data enable mii port mii_txen vo8 this pin is the transmit data enable signal to the external phy. 1 link status mii port mii_link vis this pin is the provided by the phy to indicate that a 100 mbit/s full duplex link is established. the polar- ity is configurable via the link_pol_strap_mii strap. 1 smi clock mii_mdc vo8 this pin is the serial management clock to the exter- nal phy. 1s m i d a t a mii_mdio vis/vo8 this pin is the serial management interface data input/output to the external phy. note: an external pull-up is required to ensure that the non-driven state of the mdio signal is a logic one. downloaded from: http:///
lan9252 ds00001909a-page 22 ? 2015 microchip technology inc. table 3-7: host bus pin descriptions num pins name symbol buffer type description 1 read rd vis this pin is the host bus read strobe. normally active low, the polarity can be changed via the hbi read, read/write polarity bit of the pdi configuration register (hbi modes). read or write rd_wr vis this pin is the host bus direction control. used in conjunction with the enb pin, it indicates a read or write operation. the normal polarity is read when 1, write when 0 (r/ nw) but can be changed via the hbi read, read/ write polarity bit of the pdi configuration register (hbi modes). 1 write wr vis this pin is the host bus write strobe. normally active low, the polarity can be changed via the hbi write, enable polarity bit of the pdi config- uration register (hbi modes). enable enb vis this pin is the host bus data enable strobe. used in conjunction with the rd_wr pin it indicates the data phase of the operation. normally active low, the polarity can be changed via the hbi write, enable polarity bit of the pdi config- uration register (hbi modes). 1 chip select cs vis this pin is the host bus chip select and indicates that the device is select ed for the current transfer. normally active low, the polarity can be changed via the hbi chip select polarity bit of the pdi configu- ration register (hbi modes). 5a d d r e s s a[4:0] vis these pins provide the address for non-multiplexed address mode. in 16-bit data mode, bit 0 is not used. downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 23 lan9252 16 data d[15:0] vis/vo8 these pins are the host bus data bus for non-multi- plexed address mode. in 8-bit data mode, bits 15-8 are not used and their input and output drivers are disabled. address & data ad[15:0] vis/vo8 these pins are the host bus address / data bus for multiplexed address mode. bits 15-8 provide the upper byte of address for sin- gle phase multiplexed address mode. bits 7-0 provide the lower byte of address for single phase multiplexed address mode and both bytes of address for dual phase multiplexed address mode. in 8-bit data dual phase multiplexed address mode, bits 15-8 are not used and their input and output drivers are disabled. 1 address latch enable high alehi vis this pin indicates the address phase for multiplexed address modes. it is used to load the higher address byte in dual phase multiplexed address mode. normally active low (address saved on rising edge), the polarity can be changed via the hbi ale polar- ity bit of the pdi configuration register (hbi modes). 1 address latch enable low alelo vis this pin indicates the address phase for multiplexed address modes. it is used to load both address bytes in single phase multiplexed address mode and the lower address byte in dual phase multi- plexed address mode. normally active low (address saved on rising edge), the polarity can be changed via the hbi ale polar- ity bit of the pdi configuration register (hbi modes). table 3-7: host bus pin descriptions (continued) num pins name symbol buffer type description downloaded from: http:///
lan9252 ds00001909a-page 24 ? 2015 microchip technology inc. note 9: although this pin is an output for spi instructions , it includes a pull-up since it is also sio bit 1. table 3-8: spi/sqi pin descriptions num pins name symbol buffer type description 1 spi/sqi slave chip select scs# vis (pu) this pin is the spi/sqi slave chip select input. when low, the spi/sqi slave is selected for spi/sqi transfers. when high, the spi/sqi serial data out- put(s) is(are) 3-stated. 1 spi/sqi slave serial clock sck vis (pu) this pin is the spi/sqi slave serial clock input. 4 spi/sqi slave serial data input/output sio[3:0] vis/vo8 (pu) these pins are the spi/sqi slave data input and output for multiple bit i/o. spi slave serial data input si vis (pu) this pin is the spi slave serial data input. si is shared with the sio0 pin. spi slave serial data output so vo8 (pu) note 9 this pin is the spi slave serial data output. so is shared with the sio1 pin. table 3-9: ethercat distribut ed clock pin descriptions num pins name symbol buffer type description 2 sync sync[1] sync[0] vo8 these pins are the distributed clock sync (out) or latch (in) signals. the direction is bitwise configurable. note: these signals are not driven (high impedance) until the eeprom is loaded. latch latch[1] latch[0] vis table 3-10: ethercat digital i/o and gpio pin descriptions num pins name symbol buffer type description 16 general purpose input gpi[15:0] vis these pins are the general purpose inputs and are directly mapped into the general purpose inputs register . consistency of the general purpose inputs is not provided. general purpose output gpo[15:0] vo8 these pins are the general purpose outputs and reflect the values of the general purpose outputs register without watchdog protection. note: these signals are not driven (high impedance) until the eeprom is loaded. 16 digital i/o digio[15:0] vis/vo8 these pins are the input/output or bidirectional data. note: these signals are not driven (high impedance) until the eeprom is loaded. 1 output valid outvalid vo8 this pin indicates that the outputs are valid and can be captured into external registers. note: the signal is not driven (high imped- ance) until the eeprom is loaded. downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 25 lan9252 1l a t c h i n latch_in vis this pin is the external data latch signal. the input data is sampled each time a rising edge of latch_in is recognized. 1 watchdog trigger wd_trig vo8 this pin is the syncmanager watchdog trigger out- put. note: the signal is not driven (high imped- ance) until the eeprom is loaded. 1 watchdog state wd_state vo8 this pin is the syncmanager watchdog state out- put. a 0 indicates the watchdog has expired. note: the signal is not driven (high imped- ance) until the eeprom is loaded. 1 start of frame sof vo8 this pin is the start of frame output and indicates the start of an ethe rnet/ethercat frame. note: the signal is not driven (high imped- ance) until the eeprom is loaded. 1 end of frame eof vo8 this pin is the end of frame output and indicates the end of an ethernet/ethercat frame. note: the signal is not driven (high imped- ance) until the eeprom is loaded. 1 output enable oe_ext vis this pin is the output enable input. when low, it clears the output data. table 3-11: eeprom pin descriptions num pins name symbol buffer type description 1 eeprom i 2 c serial data input/output eesda vis/vod8 when the device is accessing an external eeprom this pin is the i 2 c serial data input/open-drain out- put. note: this pin must be pulled-up by an exter- nal resistor at all times. 1 eeprom i 2 c serial clock eescl vod8 when the device is accessing an external eeprom this pin is the i 2 c clock open-drain output. note: this pin must be pulled-up by an exter- nal resistor at all times. table 3-10: ethercat digital i/o an d gpio pin descriptions (continued) num pins name symbol buffer type description downloaded from: http:///
lan9252 ds00001909a-page 26 ? 2015 microchip technology inc. table 3-12: led & configurat ion strap pin descriptions num pins name symbol buffer type description 1 link/activity led port 2 linkactled2 vod12/ vos12 this pin is the link/activity led output (off=no link, on=link without activity, blinking=link and activity) for port 2. this pin is configured to be an open-drain/open- source output. the choice of open-drain vs. open- source as well as the polarity of this pin depends upon the strap value sampled at reset. note: refer to section 12.10, "leds," on page 208 to additional information. mii port link polarity configuration strap mii_linkpol vis (pu) this strap configures the polarity of the mii_link pin by setting the value of link_pol_strap_mii . see note 10 . 1 run led runled vod12/ vos12 this pin is the run led output and is controlled by the al status register . this pin is configured to be open-drain/open-source output. the choice of open- drain vs. open-source as well as the polarity of this pin depends upon the strap value sampled at reset. note: refer to section 12.10, "leds," on page 208 to additional information. eeprom size configuration strap e2psize vis (pu) this strap configures the value of the eeprom size hard-strap. see note 10 . a low selects 1k bits (128 x 8) through 16k bits (2k x 8). a high selects 32k bits (4k x 8) through 4mbits (512k x 8). 1 link / activity led port 1 linkactled1 vod12/ vos12 this pin is the link/activity led output (off=no link, on=link without activity, blinking=link and activity) for port 1. this pin is configured to be open-drain/open-source output. the choice of open- drain vs. open-source as well as the polarity of this pin depends upon the strap value sampled at reset. note: refer to section 12.10, "leds," on page 208 to additional information. chip mode configuration strap 1 chip_mode1 vis (pu) this strap, along with chip_mode0 , configures the value of the chip mode hard-strap. see note 10 . downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 27 lan9252 note 10: configuration strap pins are ident ified by an underlined symbol name . configuration strap values are latched on power-on reset or rst# de-assertion. refer to section 7.0, "configuration straps," on page 51 for more in formation. 1 link / activity led port 0 linkactled0 vod12/ vos12 this pin is the link/activity led output (off=no link, on=link without activity, blinking=link and activity) for port 0. this pin is configured to be open-drain/open-source output. the choice of open- drain vs. open-source as well as the polarity of this pin depends upon the strap value sampled at reset. note: refer to section 12.10, "leds," on page 208 to additional information. chip mode configuration strap 0 chip_mode0 vis (pu) this strap, along with chip_mode1 , configures the value of the chip mode hard-strap. see note 10 . table 3-13: miscellaneous pin descriptions num pins name symbol buffer type description 1 interrupt output irq vo8/vod8 interrupt request output. the polarity, source and buffer type of this signal is programmable via the interrupt configuration register (irq_cfg) . for more information, refer to section 8.0, "system interrupts," on page 53 . 1 system reset input rst# vis/vod8 (pu) as an input, this active low signal allows external hardware to reset the device. the device also con- tains an internal power-on reset circuit. thus this signal may be left unconnected if an external hard- ware reset is not needed. when used this signal must adhere to the reset timing requirements as detailed in the section 18.0, "operational character- istics," on page 307 . as an output, this signal is driven low during por or in response to an et hercat reset command sequence from the master c ontroller or host inter- face. 1 regulator enable reg_en ai when tied to 3.3 v, the internal 1.2 v regulators are enabled. 1 test mode testmode vis (pd) this pin must be tied to vss for proper operation. 1 crystal input osci iclk external 25 mhz crystal input. this signal can also be driven by a single-ended clock oscillator. when this method is used, osco should be left uncon- nected. 1 crystal output osco oclk external 25 mhz crystal output. 1 crystal +1.2 v power supply oscvdd12 p supplied by the on-chip regulator unless configured for regulator off mode via reg_en . 1 crystal ground oscvss p crystal ground. table 3-12: led & configuration st rap pin descriptions (continued) num pins name symbol buffer type description downloaded from: http:///
lan9252 ds00001909a-page 28 ? 2015 microchip technology inc. note 11: refer to section 4.0, "power connections," on page 29 , the device reference schematic, and the device lancheck schematic checklist for additional connection information. table 3-14: jtag pin descriptions num pins name symbol buffer type description 1 jtag test mux select tms vis jtag test mode select 1 jtag test clock tck vis jtag test clock 1 jtag test data input tdi vis jtag data input 1 jtag test data output tdo vo12 jtag data output table 3-15: core and i/o power pin descriptions num pins name symbol buffer type description 1 regulator +3.3 v power supply vdd33 p +3.3 v power supply for internal regulators. see note 11 . note: +3.3 v must be supplied to this pin even if the internal regulators are disabled. 5 +1.8 v to +3.3 v variable i/o power vddio p +1.8 v to +3.3 v variable i/o power. see note 11 . 3 +1.2 v digital core power supply vddcr p supplied by the on-chip regulator unless configured for regulator off mode via reg_en . 1 f and 470 pf decoupling capacitors in parallel to ground should be used on pin 6. see note 11 . 1 pad ground vss p common ground. this exposed pad must be con- nected to the ground plane with a via array. downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 29 lan9252 4.0 power connections figure 4-1 and figure 4-2 illustrate the device power connections for regulator enabled and disabled cases, respec- tively. refer to the device reference schematic and the de vice lancheck schematic check list for additional information. section 4.1 provides additional information on the devices internal voltage regulators. figure 4-1: power connecti ons - regulators enabled +1.8 v to +3.3 v vddcr core logic & phy digital vdd12tx2 ethernet phy 1 analog 1.0 f 0.1 ? esr vdd33bias vdd33txrx1 vss vddcr ethernet phy 2 analog vdd12tx1 vdd33txrx2 ethernet master bias io pads to phy1 magnetics to phy2 magnetics note: bypass and bulk caps as needed for pcb vddio vdd33 +3.3 v +3.3 v 470 pf crystal oscillator vss pll (exposed pad) (or separate 2.5v) (or separate 2.5v) vddio vddio vddio vddio vddcr oscvdd12 oscvss +3.3 v (in) +1.2 v (out) internal 1.2 v core regulator enable +3.3 v (in) +1.2 v (out) internal 1.2 v oscillator regulator vss enable reg_en (pin 6) downloaded from: http:///
lan9252 ds00001909a-page 30 ? 2015 microchip technology inc. figure 4-2: power connections - regulators disabled +1.8 v to +3.3 v vddcr core logic & phy digital vdd12tx2 ethernet phy 1 analog vdd33bias vdd33txrx1 vss vddcr ethernet phy 2 analog vdd12tx1 vdd33txrx2 ethernet master bias io pads to phy1 magnetics to phy2 magnetics note: bypass and bulk caps as needed for pcb vddio vdd33 +3.3 v +3.3 v crystal oscillator vss pll (exposed pad) (or separate 2.5v) (or separate 2.5v) vddio vddio vddio vddio vddcr oscvdd12 oscvss +3.3 v (in) +1.2 v (out) internal 1.2 v core regulator enable +3.3 v (in) +1.2 v (out) internal 1.2 v oscillator regulator vss enable reg_en +1.2 v (pin 6) downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 31 lan9252 4.1 internal voltage regulators the device contains two internal 1.2 v regulators: 1.2 v core regulator 1.2 v crystal oscillator regulator 4.1.1 1.2 v core regulator the core regulator supplies 1.2 v volts to the main core digital logic, the i/o pads, and the phys digital logic and can be used to supply the 1.2 v power to the phy analog sections (via an external connection). when the reg_en input pin is connected to 3.3 v, the core regulator is enabled and receives 3.3 v on the vdd33 pin. a 1.0 uf 0.1 ? esr capacitor must be connected to the vddcr pin associated with the regulator. when the reg_en input pin is connected to vss , the core regulator is disabled. however, 3.3 v must still be supplied to the vdd33 pin. the 1.2 v core voltage must then be externally input into the vddcr pins. 4.1.2 1.2 v crystal oscillator regulator the crystal oscillator regulator supplies 1.2 v volts to the crystal oscillator. when the reg_en input pin is connected to 3.3 v, the crystal oscillator regulator is enabled and receives 3.3 v on the vdd33 pin. an external capacitor is not required. when the reg_en input pin is connected to vss , the crystal oscillator regulator is disabled. however, 3.3 v must still be supplied to the vdd33 pin. the 1.2 v crystal oscillator volta ge must then be externally input into the oscvdd12 pin. downloaded from: http:///
lan9252 ds00001909a-page 32 ? 2015 microchip technology inc. 5.0 register map this chapter details the device regist er map and summarizes the various dire ctly addressable system control and sta- tus registers (csrs). detailed descriptions of the system csrs are provid ed in the chapters corresponding to their function. additional indi rectly addressable registers are available in the vari ous sub-blocks of the device. these regis- ters are also detailed in their corresponding chapters. directly addressable registers section 12.13, "ethercat csr and process data ram a ccess registers (directly addressable)," on page 214 section 5.1, "system control an d status registers," on page 34 indirectly addressable registers section 11.2.16, "phy registers," on page 142 section 12.14, "ethercat core csr regist ers (indirectly addressable)," on page 223 figure 5-1 contains an overall base register memory map of t he device. this memory map is not drawn to scale, and should be used for general reference only. table 5-1 provides a summary of all directly addressable csrs and their corresponding addresses. note: register bit type definitions are provided in section 1.3, "register nomenclature," on page 7 . not all device registers are memory mapped or directly addressable. for details on the accessibility of the various device registers, refer the register sub- sections listed above. downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 33 lan9252 figure 5-1: register address map 000h 020h 300h 314h03ch 01ch ethercat process ram read fifo ethercat process ram write fifo test 0e0h 0fch ethercat 318h 3ffh interrupts 054h 05ch gp timer and free run counter 09ch08ch note: not all registers are shown downloaded from: http:///
lan9252 ds00001909a-page 34 ? 2015 microchip technology inc. 5.1 system control and status registers the system csrs are directly addressable memory mapped registers with a base address offs et range of 050h to 314h. these registers are addressable by the host via the host bus interface (hbi) or spi/sqi . for more information on the various device modes and their corresponding address configurations, see section 2.0, "general description," on page 8 . table 5-1 lists the system csrs and their corresponding addresses in order. all system csrs are reset to their default value on the assertion of a chip-level reset. the system csrs can be divided into the following sub-categor ies. each of these sub-categories is located in the cor- responding chapter and contains the system csr descriptions of the associated registers. the register descriptions are categorized as follows: section 6.2.3, "reset registers," on page 42 section 6.3.5, "power manag ement registers," on page 47 section 8.3, "interrupt registers," on page 56 section 12.13, "ethercat csr and process data ram a ccess registers (directly addressable)," on page 214 section 16.1, "miscellaneous system conf iguration & status registers," on page 301 note: unlisted registers are reserved for future use. table 5-1: system control and status registers address register name (symbol) 000h-01ch ethercat process ram read data fifo (ecat_pram_rd_data) 020h-03ch ethercat process ram write data fifo (ecat_pram_wr_data) 050h chip id and revision (id_rev) 054h interrupt configuration register (irq_cfg) 058h interrupt status register (int_sts) 05ch interrupt enable register (int_en) 064h byte order test register (byte_test) 074h hardware configuration register (hw_cfg) 084h power management control register (pmt_ctrl) 08ch general purpose timer config uration register (gpt_cfg) 090h general purpose timer count register (gpt_cnt) 09ch free running 25mhz counter register (free_run) reset register 1f8h reset control register (reset_ctl) ethercat registers 300h ethercat csr interface data register (ecat_csr_data) 304h ethercat csr interface command register (ecat_csr_cmd) 308h ethercat process ram read address and length register (ecat_pram_rd_addr_len) 30ch ethercat process ram read command register (ecat_pram_rd_cmd) 310h ethercat process ram write address and length register (ecat_pram_wr_addr_len) 314h ethercat process ram write comm and register (ecat_pram_wr_cmd) downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 35 lan9252 5.2 special restrictions on back-to-back cycles 5.2.1 back-to-back write-read cycles it is important to note that there are sp ecific restrictions on the timing of back-to -back host write-read operations. these restrictions concern reading registers af ter any write cycle that may affect the register. in all cases there is a delay between writing to a register and the new value becoming available to be read. in other cases, there is a delay between writing to a register and the subseque nt side effect on other registers. in order to prevent the host from reading stale data after a write operation, minimum wait periods have been established. these periods are specified in ta b l e 5 - 2 . the host processor is required to wait t he specified period of time after writing to the indicated register before reading the resource specified in the table. no te that the required wait period is depen- dent upon the register being read after the write. performing dummy reads of the byte order test register (byte_test) register is a convenient way to guarantee that the minimum write-to-read ti ming restriction is met. ta b l e 5 - 2 shows the number of dummy reads that are required before reading the register in dicated. the number of byte_ test reads in this table is based on the minimum cycle timing of 45ns. for microprocessors with slower busses the number of reads may be reduced as long as the total time is equal to, or greater than the time specified in the tabl e. note that dummy reads of the byte_test register are not required as long as the minimum time period is met. note that depending on the host interface mode in use, th e basic host interface cycle may naturally provide sufficient time between writes and read. it is required of the system design and register access mechanisms to ensure the proper timing. for example, a wr ite and read to the same register may occur fa ster than a write and read to different registers. for 8 and 16-bit write cycles, the wait ti me for the back-to-back write-read operat ion applies only to the writing of the last byte or word of the register, wh ich completes a single dword transfer. for indexed address mode hbi operation, the wait time for the back-to-ba ck write-read operation applies only to access to the internal registers and fifos. it does not apply to the host bus interface index registers or the host bus interface configuration register. table 5-2: read after write timing rules after writing... wait for this many nanoseconds... or perform this many reads of byte_test (assuming t cyc of 45ns) before reading... any register 45 1 the same register or any other register affected by the write interrupt configuration regis- ter (irq_cfg) 60 2 interrupt configuration regis- ter (irq_cfg) interrupt enable register (int_en) 90 2 interrupt configuration regis- ter (irq_cfg) 60 2 interrupt status register (int_sts) interrupt status register (int_sts) 180 4 interrupt configuration regis- ter (irq_cfg) 170 4 interrupt status register (int_sts) power management control register (pmt_ctrl) 165 4 power management control register (pmt_ctrl) 170 4 interrupt configuration regis- ter (irq_cfg) 160 4 interrupt status register (int_sts) downloaded from: http:///
lan9252 ds00001909a-page 36 ? 2015 microchip technology inc. 5.2.2 back-to-back read cycles there are also restrictions on specific back-to-back host re ad operations. these restrictions concern reading specific registers after reading a resource that has side effects. in many cases there is a delay between reading the device, and the subsequent indication of the expected change in the control and status register values. in order to prevent the host from reading stale data on back-to-back reads, minimum wait periods have been estab- lished. these periods are specified in table 5-3 . the host processor is required to wait the specified period of time between read operations of specific combinations of res ources. the wait period is dependent upon the combination of registers being read. performing dummy reads of the byte order test register (byte_test) register is a convenient way to guarantee that the minimum wait time restriction is met. table 5-3 below also shows the number of dummy reads that are required for back-to-back read operations. the number of byte_test read s in this table is based on the minimum timing for t cyc (45ns). for microprocessors with slower busses the number of reads may be reduced as long as the total time is equal to, or greater than the time specified in the table. dummy reads of the byte_t est register are not required as long as the minimum time period is met. note that depending on the host interface mode in use, th e basic host interface cycle may naturally provide sufficient time between reads. it is required of the system design and register access mechanisms to ensure the proper timing. for example, multiple reads to the same register may occur faster than reads to different registers. for 8 and 16-bit r ead cycles, the wait time fo r the back-to-back read oper ation is required only after the reading of the last byte or word of the register, which completes a sing le dword transfer. there is no wait requirement between the byte or word accesses within the dword transfer. general purpose timer con- figuration register (gpt_cfg) 55 2 general purpose timer con- figuration register (gpt_cfg) 170 4 general purpose timer count register (gpt_cnt) ethercat process ram write data fifo (ecat_pram_wr_data) 50 2 ethercat process ram write command register (ecat_pram_wr_cmd) table 5-3: read after read timing rules after reading... wait for this many nanoseconds... or perform this many reads of byte_test (assuming t cyc of 45ns) before reading... ethercat process ram read data fifo (ecat_pram_rd_data) 50 2 ethercat process ram read command register (ecat_pram_rd_cmd) table 5-2: read after write timing rules (continued) after writing... wait for this many nanoseconds... or perform this many reads of byte_test (assuming t cyc of 45ns) before reading... downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 37 lan9252 6.0 clocks, resets, a nd power management 6.1 clocks the device provides generation of all sys tem clocks as required by the various sub-modules of the device. the clocking sub-system is comprised of the following: crystal oscillator phy pll 6.1.1 crystal oscillator the device requires a fixed-frequency 25 mhz clock source for use by the internal clock oscillator and pll. this is typ- ically provided by attaching a 25 mhz crystal to the osci and osco pins as specified in section 18.7, "clock circuit," on page 320 . optionally, this clock can be provided by driving the osci input pin with a single-ended 25 mhz clock source. if a single-ended source is sele cted, the clock input must run continuous ly for normal device operation. power savings modes allow for the oscillator or external clock input to be halted. the crystal oscillator can be disabled as describe in section 6.3.4, "chip level power management," on page 45 . for system level verificati on, the crystal oscillator output ca n be enabled onto the irq pin. see section 8.2.7, "clock output test mode," on page 56 . power for the crystal oscillator is provided by a dedicated regulator or separate input pin. see section 4.1.2, "1.2 v crys- tal oscillator regulator," on page 31 . 6.1.2 phy pll the phy module receives the 25 mhz reference clock and, in addition to its internal clock usage, outputs a main system clock that is used to de rive device sub-system clocks. the phy pll can be disabled as describe in section 6.3.4, "chip level power management," on page 45 . the phy pll will be disabled only when requested and if the phy ports are in a power down mode. power for phy pll is provided by an external input pin, us ually sourced by the devices 1.2v core regulator. see section 4.0, "power connections," on page 29 . note: crystal specifications are provided in table 18-12, crystal specifications, on page 320 . downloaded from: http:///
lan9252 ds00001909a-page 38 ? 2015 microchip technology inc. 6.2 resets the device provides multiple hardware and software reset s ources, which allow varying levels of the device to be reset. all resets can be categorized into three reset types as described in the following sections: chip-level resets - power-on reset (por) - rst# pin reset - ethercat system reset multi-module resets - digital reset (digital_rst) single-module resets - port a phy reset - port b phy reset - ethercat controller reset the device supports the use of configuratio n straps to allow automatic custom configurations of various device param- eters. these configurati on strap values are set upon de-assertion of all chip-level resets and can be used to easily set the default parameters of the chip at power-on or pin (rst#) reset. refer to section 6.3, "power management," on page 43 for detailed information on the usage of these straps. table 6-1 summarizes the effect of the various reset sources on the device. refer to the following sections for detailed information on each of these reset types. table 6-1: reset sources and affected device functionality module/ functionality por rst# pin ethercat system reset digital reset ethercat module reset 25 mhz oscillator ( 1 ) voltage regulators ( 2 ) ethercat core xxxxx phy a xxx phy b xxx phy common ( 3 ) voltage supervision ( 3 ) pll ( 3 ) spi/sqi slave xxxx host bus interface xxxx power management xxxx general purpose timer xxxx free running counter xxxx system csr xxxx config. straps latched yes yes yes no( 4 ) eeprom loader run yes yes yes yes yes tristate output pins ( 5 ) yes yes yes rst# pin driven low yes yes note 1: por is performed by the xtal voltage regulator, not at the system level 2: por is performed internal to the voltage regulators 3: por is performed internal to the phy 4: strap inputs are not re-latched 5: only those output pins that are used for straps downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 39 lan9252 6.2.1 chip-level resets a chip-level reset event activates all internal resets, effectiv ely resetting the entire device. a chip-level reset is initiate d by assertion of any of the following input events: power-on reset (por) rst# pin reset ethercat system reset chip-level reset/configuration completion can be determined by first polling the byte order test register (byte_test) . the returned data will be invalid until the host interface resets are complete. once the returned data is the correct byte ordering value, the host interface resets have completed. the completion of the entire chip-level reset mu st be determined by polling the ready bit of the hardware configura- tion register (hw_cfg) or power management control register (pmt_ctrl) until it is set. when set, the ready bit indicates that the reset has completed and the device is ready to be accessed. with the exception of the hardware configuration register (hw_cfg) , power management control register (pmt_c- trl) , byte order test register (byte_test) , and reset control register (reset_ctl) , read access to any internal resources should not be done by s/w while the ready bit is cl eared. writes to any addre ss are invalid until the ready bit is set. a chip-level reset involves tuning of the variable output le vel pads, latching of configuration straps and generation of the master reset. configuration straps latching during por, ethercat reset or rst# pin reset, the latches for the straps ar e open. following the release of por, eth- ercat reset or rst# pin reset, the latches for the straps are closed. variable level i/o pad tuning following the release of the ethercat, por or rst# pin resets, a 1 us pulse (active lo w), is sent into the vo tuning circuit. 2 us later, the output pins are enabled. the 2 us delay al lows time for the variable output level pins to tune before enabling the outputs and also provides input hold time for strap pins that are s hared with output pins. master reset and clock generation reset following the enabling of the output pins, the rese t is synchronized to the main syst em clock to become the master reset. master reset is used to generate the lo cal resets and to reset the clocks generation. 6.2.1.1 power-on reset (por) a power-on reset occurs whenever power is initially applied to the device or if the power is removed and reapplied to the device. this event resets all circuitry within the dev ice. configuration straps are latched and eeprom loading is performed as a result of this reset. the por is used to tr igger the tuning of the variable level i/o pads as well as a chip-level reset. the por can also used as a system level reset. rst# becomes an open-drain output and is asserted for the por time. its purpose is to perform a complete rese t of the ethercat slave and/or to hold an external phy in reset while the eth- ercat core is in reset. as an open- drain output, rst is in tended to be wired ord into the system reset. following valid voltage levels, a por reset typically takes approximately 21 ms. 6.2.1.2 rst# pin reset driving the rst# input pin low initiates a chip-level reset. this event resets all circuitry within the device. use of this reset input is optional, but when used, it must be driven for the period of time specified in section 18.6.3, "reset and configuration strap timing," on page 317 . configuration straps are latched, and eeprom loading is performed as a result of this reset. note: the ethernet phy should be connected to the rst# pin so that the phy is held in reset until the ethercat slave is ready. otherwise, the far end link partner would detect valid link signals from the phy and would open its port assuming that the local ethercat slave was ready. the rst# pin is not driven until all vo ltages are operational. external, system level solutions are necessary if the system needs to be held in reset during power ramp-up. downloaded from: http:///
lan9252 ds00001909a-page 40 ? 2015 microchip technology inc. a rst# pin reset typically takes approximately 760 ? s. please refer to table 3-13, miscellaneous pin descriptions, on page 27 for a description of the rst# pin. 6.2.1.3 ethercat system reset an ethercat system reset, initiated by a special sequ ence of three independent and consecutive frames/commands, is functionally identical to a rst# pin reset, except that during an ethe rcat system reset, the rst# pin becomes an open-drain output and is asserted for the minimum required time of 80 ms. the rst# is an open-drain output intended to be wired ord into the system reset. 6.2.2 block-level resets the block level resets co ntain an assortment of reset regi ster bit inputs and generate resets for the various blocks. block level resets can affect one or multiple modules. 6.2.2.1 multi-module resets multi-module resets activate multiple internal resets, but do not reset the entire ch ip. configuration straps are not latched upon multi-module resets. a multi-module reset is initiated by assertion of the following: digital reset (digital_rst) multi-module reset/configuration completion can be determined by first polling the byte order test register (byte_test) . the returned data will be invalid until the host interface resets are complete. once the returned data is the correct byte ordering value, the ho st interface resets have completed. the completion of the entire chip-level reset mu st be determined by polling the ready bit of the hardware configura- tion register (hw_cfg) or power management control register (pmt_ctrl) until it is set. when set, the ready bit indicates that the reset has completed and the device is ready to be accessed. with the exception of the hardware configuration register (hw_cfg) , power management control register (pmt_c- trl) , byte order test register (byte_test) , and reset control register (reset_ctl) , read access to any internal resources should not be done by s/w while the ready bit is cleared. writes to any address are invalid until the ready bit is set. digital reset (digital_rst) a digital reset is performed by setting the digital_rst bit of the reset control register (reset_ctl) . a digital reset will reset all device sub-modules except the ethernet phys . eeprom loading is performed following this reset. con- figuration straps are not latched as a result of a digital reset. a digital reset typically takes approximately 760 ? s. 6.2.2.2 single-module resets a single-module reset will reset only the specified module. single-module resets do not latch the configuration straps. a single-module reset is initiated by assertion of the following: port a phy reset port b phy reset ethercat controller reset note: the rst# pin is pulled-high internally. if unused, this signal can be left unconnected. do not rely on internal pull-up resistors to drive signals external to the device. note: the purpose of connecting the rst# pin into the system reset is to per form a complete reset of the ether- cat slave. the ethercat master issues this reset in rare and extreme cases when the local microcontrol- ler is seriously halted and can not be otherwise informed to reinitialize. note: the digital reset does not reset register bits designated as nasr. downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 41 lan9252 port a phy reset a port a phy reset is performed by setting the phy_a_rst bit of the reset control regi ster (reset_ctl) or the soft reset bit in the phy x basic control register (phy_basic_control_x) . upon completion of the port a phy reset, the phy_a_rst and soft reset bits are automatically cleared . no other modules of the de vice are affected by this reset. port a phy reset completion can be determined by polling the phy_a_rst bit in the reset control register (reset_ctl) or the soft reset bit in the phy x basic control regist er (phy_basic_control_x) until it clears. under normal conditions, the phy_a_rst and soft reset bit will clear approximately 102 us after the port a phy reset occurrence. in addition to the methods above, the port a phy is autom atically reset after returning from a phy power-down mode. this reset differs in that the phy power-down mode reset does not reload or reset any of the phy registers. refer to section 11.2.8, "phy power-down modes," on page 131 for additional information. refer to section 11.2.10, "resets," on page 135 for additional information on port a phy resets. if port a phy is in 100base-fx mode, it is reset when the enhanced link detect ion function detects errors on port 0 (2 port mode or 3 port downstream mode) or on port 2 (3 port upstream mode). port b phy reset a port b phy reset is performed by setting the phy_b_rst bit of the reset control regi ster (reset_ctl) or the soft reset bit in the phy x basic control register (phy_basic_control_x) . upon completion of the port b phy reset, the phy_b_rst and soft reset bits are automatically cleared . no other modules of the de vice are affected by this reset. port b phy reset completion can be determined by polling the phy_b_rst bit in the reset control register (reset_ctl) or the soft reset bit in the phy x basic control regist er (phy_basic_control_x) until it clears. under normal conditions, the phy_b_rst and soft reset bit will clear approximately 102 us after the port b phy reset occurrence. in addition to the methods above, the port b phy is autom atically reset after returning from a phy power-down mode. this reset differs in that the phy power-down mode reset does not reload or reset any of the phy registers. refer to section 11.2.8, "phy power-down modes," on page 131 for additional information. refer to section 11.2.10, "resets," on page 135 for additional information on port b phy resets. if port b phy is in 100base-fx mode, it is reset when th e enhanced link detection function detects errors on port 1. ethercat controller reset a compete device and system reset can be initiated by either the ethercat master or by the local host by writing the value sequence of 0x52 (r), 0x45 (e) and 0x53 (s) into the esc reset ecat register (for the master) or the esc reset pdi register (for the local host). this wi ll trigger the reset described in section 6.2.1.3, "eth ercat system reset" . a reset of just the ethercat controller may be performed by setting the ethercat_rst bit in the reset control reg- ister (reset_ctl) . this will reset the ethercat core and its registers. it will also reset the ethercat csr and process data ram access logic described in section 12.11, on page 208 and will reset the registers described in section 12.13, "ethercat csr and process data ram access registers (directly addressable)," on page 214 . since the ethercat module will reconfigure the device from the eeprom, the host interfaces will be disabled until reset is complete. completion of the reset must be determined by using the methods described in section 9.4.2.2, on page 64 and section 9.5.3.2, on page 85 for hbi and section 10.2.1.1, on page 104 for spi/sqi. note: when using the soft reset bit to reset the port a ph y, register bits designated as nasr are not reset. note: when using the soft reset bit to reset the port b ph y, register bits designated as nasr are not reset. downloaded from: http:///
lan9252 ds00001909a-page 42 ? 2015 microchip technology inc. 6.2.3 reset registers 6.2.3.1 reset control register (reset_ctl) this register contains software controlled resets. offset: 1f8h size: 32 bits note: this register can be read while the device is in the reset or not ready / power savings states without leaving the host interface in an intermediate state. if the host interface is in a reset state, returned data may be invalid. it is not necessary to read all four bytes of this register. dword access rules do not apply to this register. bits description type default 31:7 reserved ro - 6 ethercat reset (ethercat_rst) setting this bit resets the ethercat core. when the ethercat core is released from reset, this bit is automati cally cleared. all writes to this bit are ignored while this bit is set. r/w sc 0b 5 reserved ro - 4 reserved ro - 3 reserved ro - 2 port b phy reset (phy_b_rst) setting this bit resets the port b phy. the internal logic automatically holds the phy reset for a minimum of 102us. when the port b phy is released from reset, this bit is automatically cl eared. all writes to this bit are ignored while this bit is set. r/w sc 0b 1 port a phy reset (phy_a_rst) setting this bit resets the port a phy. the internal logic automatically holds the phy reset for a minimum of 102us. when the port a phy is released from reset, this bit is automatically cl eared. all writes to this bit are ignored while this bit is set. r/w sc 0b 0 digital reset (digital_rst) setting this bit resets the complete chip except the pll, port b phy and port a phy. all system csrs are reset except for any nasr type bits. when the chip is released from reset, this bit is automat ically cleared. all writes to this bit are ignored while this bit is set. r/w sc 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 43 lan9252 6.3 power management the device supports several block and chip level power ma nagement features as well as wake-up event detection and notification. 6.3.1 wake-up event detection 6.3.1.1 phy a & b energy detect energy detect power down mode reduces phy power consum ption. in energy-detect power-down mode, the phy will resume from power-down when energy is seen on the cabl e (typically from link pulses) and set the energyon inter- rupt bit in the phy x interrupt source flags register (phy_interrupt_source_x) . refer to section 11.2.8.2, "energy detect power-down," on page 131 for details on the operation and configuration of the phy energy-detect power-down mode. if enabled, via the phy x interrupt mask register (phy_interrupt_mask_x) , the phy will generate an interrupt. this interrupt is reflected in the interrupt status register (int_sts) , bit 26 (phy_int_a) for phy a and bit 27 (phy_int_b) for phy b. the int_sts register bits will trig ger the irq interrupt output pi n if enabled, as described in section 8.2.1, "ethernet phy interrupts," on page 54 . the energy-detect phy interrupts will also set the appropriate energy-detect / wol status port a (ed_wol_sts_a) or energy-detect / wol status port b (ed_wol_sts_b) bit of the power management control register (pmt_ctrl) . the energy-detect / wol enable port a (ed_wol_en_a) and energy-detect / wol enable port b (ed_wol_en_b) bits will enable the corresponding status bits as a pme event. 6.3.1.2 phy a & b wake on lan (wol) phy a and b provide wol event detection of perfec t da, broadcast, magic packet, and wakeup frames. when enabled, the phy will detect wol events and set the wol interrupt bit in the phy x interrupt source flags reg- ister (phy_interrupt_source_x) . if enabled via the phy x interrupt mask r egister (phy_inter- rupt_mask_x) , the phy will generate an interrupt. this interrupt is reflected in the interrupt status register (int_sts) , bit 26 (phy_int_a) for phy a and bit 27 (phy_int_b) for phy b. the int_sts re gister bits will trigger the irq interrupt output pin if enabled, as described in section 8.2.1, "ethernet phy interrupts," on page 54 . refer to section 11.2.9, "wake on lan (wol)," on page 132 for details on the operation and configuration of the phy wol. the wol phy interrupts will also set the appropriate energy-detect / wol status port a (ed_wol_sts_a) or energy- detect / wol status port b (ed_wol_sts_b) bit of the power management control register (pmt_ctrl) . the energy-detect / wol enable port a (ed_wol_en_a) and energy-detect / wol enable port b (ed_wol_en_b) bits enable the corresponding status bits as a pme event. 6.3.2 wake-up (pme) notification a simplified diagram of the logic that co ntrols the pme interrupt can be seen in figure 6-1 . the pme module handles the latching of the phy b energy-detect / wol status port b (ed_wol_sts_b) bit and the phy a energy-detect / wol status port a (ed_wol_sts_a) bit in the power management control register (pmt_c- trl) . note: if a carrier is present when energy detect power down is enabled, then detection will occur immediately. note: any phy interrupt will set the above status bits. t he host should only enable the appropriate phy interrupt source in the phy x interrupt mask register (phy_interrupt_mask_x) . note: any phy interrupt will set the above status bits. t he host should only enable the appropriate phy interrupt source in the phy x interrupt mask register (phy_interrupt_mask_x) . downloaded from: http:///
lan9252 ds00001909a-page 44 ? 2015 microchip technology inc. this module also masks the status bits with the correspondi ng enable bits ( energy-detect / wol enable port b (ed_wol_en_b) and energy-detect / wol enable port a (ed_wol_en_a) ) and combines the results together to generate the power management interrupt event (pme_int) status bit in the interrupt status register (int_sts) . the pme_int status bit is then masked with the power management event interrupt enable (pme_int_en) bit and com- bined with the other interrupt sources to drive the irq output pin. when the pm_wake bit of the power management control register (pmt_ctrl) is set, the pme event will automat- ically wake up the system in certain chip level power modes, as described in section 6.3.4.2, "exiting low power modes," on page 46 . 6.3.3 block level power management the device supports software controlled clock disabling of various modules in order to reduce power consumption. 6.3.3.1 disabling the ethercat core the entire ethercat core may be disabled by setting the ecat_dis bit in the power management control register (pmt_ctrl) . as a safety precaution, in order for this bit to be se t, it must be written as a 1 two consecutive times. a write of a 0 will reset the count. note: the pme interrupt status bit (pme_int) in the in t_sts register is set regardless of the setting of pme_int_en. figure 6-1: pme interrupt signal generation note: disabling individual blocks does not automatically reset the block, it only places it into a static non-opera- tional state in order to reduce the power consumption of the device. if a block re set is not performed before re-enabling the block, then care must be taken to ensu re that the block is in a state where it can be disabled and then re-enabled. ed_wol_en_a (bit 14) of pmt_ctrl register denotes a level-triggered "sticky" status bit pme_int_en (bit 17) of int_en register pme_int (bit 17) of int_sts register irq_en (bit 8) of irq_cfg register irq other system interrupts ed_wol_sts_a (bit 16) of pmt_ctrl register phys a & b int7_mask (bit 7) of phy_interrupt_mask_a register int7 (bit 7) of phy_interrupt_source_a register polarity & buffer type logic int8_mask (bit 8) of phy_interrupt_mask_a register int8 (bit 8) of phy_interrupt_source_a register ed_wol_en_b (bit 15) of pmt_ctrl register ed_wol_sts_b (bit 17) of pmt_ctrl register int7_mask (bit 7) of phy_interrupt_mask_b register int7 (bit 7) of phy_interrupt_source_b register int8_mask (bit 8) of phy_interrupt_mask_b register int8 (bit 8) of phy_interrupt_source_b register other phy interrupts other phy interrupts pm_wake (bit 28) of pmt_ctrl register pme wake-up downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 45 lan9252 6.3.3.2 phy power down a phy may be placed into power-down as described in section 11.2.8, "phy power-down modes," on page 131 . 6.3.3.3 led pins power down all led outputs may be disabled by setting the led_dis bit in the power management control register (pmt_ctrl) open-drain / open-source leds are un-driven. push-pull leds are still driven but are set to their inactive state. 6.3.4 chip level power management the device supports power-down modes to allow applications to minimize power consumption. power is reduced by disabling the clocks as outlined in table 6-2, "power management states" . all configuration data is saved when in any power state. register contents are not af fected unless sp ecifically indicated in the register descrip- tion. there is one normal operating power state, d0, and three power saving states: d1, d2 and d3. although appropriate for various wake-up detection functions, the power states do not directly enable and are not enforced by these functions. d0 : normal mode - this is the normal mode of operation of th is device. in this mode, all functionality is available. this mode is entered automatically on any chip-level reset (por, rst# pin reset, ethercat system reset). d1 : system clocks disabled, xtal, pll a nd network clocks enabled - in this low power mode, all clocks derived from the pll clock are disabled. the network clocks rema in enabled if supplied by the phys or externally. the crystal oscillator and the pll remain enabled. exit fr om this mode may be done manually or automatically. this mode could be used for phy general power down mode, phy wol mode and phy energy detect power down mode. d2 : system clocks disabled, pll disable requested, xtal enabled - in this low power mode, all clocks derived from the pll clock are disabled. the pll is allowed to be disabled (and will disable if both of the phys are in either energy detect or general po wer down). the network clocks remain enabled if supplied by the phys or externally. the crystal oscillator remains enabled. exit from this mode may be done manually or automatically. this mode is useful for phy energy detect power down mode and phy wol mode. this mode could be used for phy general power down mode. d3 : system clocks disabled, pll disabled, xtal disabled - in this low power mode, all clocks derived from the pll clock are disabled. the pll will be disabled. external network clocks are gated off. the crystal oscillator is disabled. exit from this mode may be only be done manually. this mode is useful for phy general power down mode. the host must place the phys into ge neral power down mode by setting the power down (phy_pwr_dwn) bit of the phy x basic control regist er (phy_basic_control_x) before setting this power state. 6.3.4.1 entering low power modes to enter any of the low power modes (d1 - d3) from normal mode (d0), follow these steps: 1. write the pm_mode and pm_wake fields in the power management control register (pmt_ctrl) to their desired values 2. set the wake-up detection desired per section 6.3.1, "wake-up event detection" . 3. set the appropriate wake-up notification per section 6.3.2, "wake-up (pme) notification" . table 6-2: power management states clock source d0 d1 d2 d3 25 mhz crystal oscillator on on on off p l l o no no f f ( 2 )o f f system clocks (100 mhz, 50 mhz, 25 mhz and others) on off off off network clocks available( 1 ) available( 1 ) available( 1 )off( 3 ) note 1: if supplied by the phys or externally 2: pll is requested to be turned off and will disable if both of t he phys are in either energy detect or general power down 3: phy clocks are off, external clocks are gated off downloaded from: http:///
lan9252 ds00001909a-page 46 ? 2015 microchip technology inc. 4. ensure that the device is in a state where it can safely be placed into a low power mode (all packets transmitted, receivers disabled, packets processed / flushed, etc.) 5. set the pm_sleep_en bit in the power management control register (pmt_ctrl) . upon entering any low power mode, the device ready (ready) bit in the hardware configuration register (hw_cfg) and the power management control register (pmt_ctrl) is forced low. 6.3.4.2 exiting low power modes exiting from a low power mode can be done manually or automatically. an automatic wake-up will occur based on the events described in section 6.3.2, "wake-up (pme) notification" . auto- matic wake-up is enabled with the power management wakeup (pm_wake) bit in the power management control register (pmt_ctrl) . a manual wake-up is initiated by the host when: an hbi write ( cs and wr or cs , rd_wr and enb ) is performed to the device. al though all writes are ignored until the device has been woken and a read perfo rmed, the host should direct the write to the byte order test register (byte_test) . writes to any other addresses should not be attempted until the device is awake. an spi/sqi cycle ( scs# low and sck high) is performed to the device. alt hough all reads and writes are ignored until the device has been woken, the host should direct the use a read of the byte order test register (byte_test) to wake the device. reads and writes to an y other addresses should not be attempted until the device is awake. to determine when the host interface is functional, the byte order test re gister (byte_test) should be polled. once the correct pattern is read, the interface can be considered functional. at this point, the device ready (ready) bit in the hardware configuration register (hw_cfg) or the power management control register (pmt_ctrl) can be polled to determine when the device is fully awake. for both automatic and manual wake-up, the device ready (ready) bit will go high once the device is returned to power savings state d0 and the pll has re-stabilized. the pm_mode and pm_sleep_en fields in the power man- agement control register (pmt_ctrl) will also clear at this point. under normal conditions, the device will wake-up within 2 ms. note: the pm_mode field cannot be changed at the same time as the pm_sleep_en bit is set and the pm_sleep_en bit cannot be set at the same time that the pm_mode field is changed. note: upon entry into any of the power saving stat es the host interfac es are not functional. downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 47 lan9252 6.3.5 power management registers 6.3.5.1 power management control register (pmt_ctrl) this read-write register controls the power management features of the device. the ready state of the device be deter- mined via the device ready (ready) bit of this register. offset: 084h size: 32 bits note: this register can be read while the device is in the reset or not ready / power savings states without leaving the host interface in an intermediate state. if the host interface is in a reset state, returned data may be invalid. it is not necessary to read all four bytes of this register. dword access rules do not apply to this register. bits description type default 31:29 power management mode (pm_mode) this register field determines the chip level power management mode that will be entered when the power management sleep enable (pm_sleep_en) bit is set. 000: d0 001: d1 010: d2 011: d3 100: reserved 101: reserved 110: reserved 111: reserved writes to this field are ignored if power management sleep enable (pm_sleep_en) is also being written with a 1. this field is cleared when the device wakes up. r/w/sc 000b 28 power management sleep enable (pm_sleep_en) setting this bit enters the chip level power management mode specified with the power management mode (pm_mode) field. 0: device is not in a low power sleep state 1: device is in a low power sleep state this bit can not be written at the same time as the pm_mode register field. the pm_mode field must be set, and then this bit must be set for proper device operation. writes to this bit with a value of 1 are ignored if power management mode (pm_mode) is being written with a new value. note: although not prevented by h/w, th is bit should not be written with a value of 1 while power management mode (pm_mode) has a value of d0. this field is cleared when the device wakes up. r/w/sc 0b downloaded from: http:///
lan9252 ds00001909a-page 48 ? 2015 microchip technology inc. 27 power management wakeup (pm_wake) when set, this bit enables automatic wake-up based on pme events. 0: manual wakeup only 1: auto wakeup enabled r/w 0b 26 led disable (led_dis) this bit disables led outputs. open-dr ain / open-source leds are un-driven. push-pull leds are still driven but are set to their inactive state. 0: leds are enabled 1: leds are disabled r/w 0b 25:22 reserved ro - 21 ethercat core clock disable (ecat_dis) this bit disables the clocks for the ethercat core. 0: clocks are enabled 1: clocks are disabled in order for this bit to be set, it must be written as a 1 two consecutive times. a write of a 0 will reset the count. r/w 0b 20 reserved ro - 19:18 reserved ro - 17 energy-detect / wol status port b (ed_wol_sts_b) this bit indicates an energy detect or wol event occurred on the port b phy. in order to clear this bit, it is required that the event in the phy be cleared as well. the event sources are described in section 6.3, "power management," on page 43 . r/wc 0b 16 energy-detect / wol status port a (ed_wol_sts_a) this bit indicates an energy detect or wol event occurred on the port a phy. in order to clear this bit, it is required that the event in the phy be cleared as well. the event sources are described in section 6.3, "power management," on page 43 . r/wc 0b 15 energy-detect / wol enable port b (ed_wol_en_b) when set, the pme_int bit in the interrupt status register (int_sts) will be asserted upon an energy-detect or wol event from port b. r/w 0b 14 energy-detect / wol enable port a (ed_wol_en_a) when set, the pme_int bit in the interrupt status register (int_sts) will be asserted upon an energy-detect or wol event from port a. r/w 0b 13:10 reserved ro - 9 reserved ro - 8:7 reserved ro - 6:5 reserved ro - bits description type default downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 49 lan9252 4 reserved ro - 3:1 reserved ro - 0 device ready (ready) when set, this bit indicates that the device is ready to be accessed. upon power-up, rst# reset, retu rn from power savings stat es, ethercat chip level or module level reset, or digital reset, the host processor may interrogate this field as an indication that the device has stabilized and is fully active. this rising edge of this bit will assert the device ready (ready) bit in int_sts and can cause an interrupt if enabled. note: with the exception of the hw_cfg, pmt_ctrl, byte_test, and reset_ctl registers, read access to any internal resources is forbidden while the ready bit is cleared. writes to any address are invalid until this bit is set. note: this bit is identical to bit 27 of the hardware configuration register (hw_cfg) . ro 0b bits description type default downloaded from: http:///
lan9252 ds00001909a-page 50 ? 2015 microchip technology inc. 6.4 device ready operation the device supports a ready status register bit that indicates to the host softwa re when the device is fully ready for operation. this bit may be read via the power management contro l register (pmt_ctrl) or the hardware configura- tion register (hw_cfg) . following power-up reset, rst# reset, ethercat chip level reset or digital reset (see section 6.2, "resets" ), the device ready (ready) bit indicates that the device has read, and is configured from, the contents of the eeprom. an ethercat reset via the reset control regi ster (reset_ctl) will cause the ethercat core to reload from the eeprom, temporarily causing the device ready (ready) to be low. entry into any power savings state (see section 6.3.4, "chip level power management" ) other than d0 will cause device ready (ready) to be low. upon wake-up, the device ready (ready) bit will go high once the device is returned to power savings state d0 and the pll has re-stabilized. downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 51 lan9252 7.0 configuration straps configuration straps allow various featur es of the device to be automatically configured to user defined values. hard- straps are latched upon power-on reset (por), ethercat reset, or pin reset ( rst# ). configuration straps include internal resistors in order to pr event the signal from floating w hen unconnected. if a partic- ular configuration strap is connected to a load, an external pull-up or pull-down resistor should be used to augment the internal resistor to ensure that it reaches the required volt age level prior to latching. the internal resistor can also be overridden by the addition of an external resistor. 7.1 hard-straps hard-straps are latched upon power-on reset (por), ethercat reset, or pin reset ( rst# ) only. these straps are used as either direct configuration values or as register defaults. ta b l e 7 - 1 provides a list of all hard-straps and their associ- ated pin. these straps, along with their pin assignments are also fully defined in section 3.0, "pin descriptions and con- figuration," on page 11 . note: the system designer must guarantee that configurati on strap pins meet the timi ng requirements specified in section 18.6.3, "reset and configuration strap timing" . if configuration strap pins are not at the correct voltage level prior to being latched, the dev ice may capture incorrect strap values. table 7-1: hard-strap config uration strap definitions strap name description pins eeprom_size_strap eeprom size strap: configures the eeprom size range. a low selects 1k bits (128 x 8) through 16k bits (2k x 8). a high selects 32k bits (4k x 8) through 4mbits (512k x 8). e2psize chip_mode_strap[1:0] ethercat chip mode strap: this strap determines the number of active ports and port types. 00 = 2 port mode. ports 0 and 1 are connected to inter- nal phys a and b. 01 = reserved 10 = 3 port downstream mode. ports 0 and 1 are con- nected to internal phys a and b. port 2 is connected to the external mii pins. 11 = 3 port upstream mode. ports 2 and 1 are connected to internal phys a and b. port 0 is connected to the external mii pins. chip_mode1 , chip_mode0 link_pol_strap_mii ethercat mii port link polarity strap: this strap deter- mines the polarity of the mii_link pin. 0 = mii_link low means a 100 mbit/s full duplex link is established 1= mii_link high means a 100 mbit/s full duplex link is established mii_linkpol downloaded from: http:///
lan9252 ds00001909a-page 52 ? 2015 microchip technology inc. tx_shift_strap[1:0] ethercat mii port tx timing shift strap: these straps determine the value of the mii tx timing shift for the mii port. 00 = 0ns 01 = 10ns 10 = 20ns 11 = 30ns tx_shift[1:0] fx_mode_strap_1 phy a fx mode strap: selects fx mode for phy a. this strap is set high when fxlosen is above 1 v (typ.) or fxsdena is above 1 v (typ.). fxlosen : fxsdena fx_mode_strap_2 phy b fx mode strap: selects fx mode for phy b. this strap is set high when fxlosen is above 2 v (typ.) or fxsdenb is above 1 v (typ.). fxlosen : fxsdenb fx_los_strap_1 phy a fx-los select strap: selects loss of signal mode for phy a. this strap is set high when fxlosen is above 1 v (typ.). fxlosen fx_los_strap_2 phy b fx-los select strap: selects loss of signal mode for phy b. this strap is set high when fxlosen is above 2 v (typ.). fxlosen table 7-1: hard-strap co nfiguration strap definitions (continued) strap name description pins downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 53 lan9252 8.0 system interrupts 8.1 functional overview this chapter describes the system interrupt structure of the device. the device provides a multi-tier programmable inter- rupt structure which is controlled by the system interrupt controller. the pr ogrammable system interrupts are generated internally by the various device sub-modules and can be config ured to generate a single external host interrupt via the irq interrupt output pin. the programmabl e nature of the host interr upt provides the user with the ability to optimize performance dependent upon the application requirements. the irq interrupt buffer type, polarity and de-assertion interval are modifiable. the irq interrupt can be configured as an open-drain output to facilitate the sharing of interrupts with other devices. all internal interrupts are maskable and capable of triggering the irq interrupt. 8.2 interrupt sources the device is capable of generating the following interrupt types: ethernet phy interrupts power management interrupts general purpose timer interrupt (gpt) ethercat interrupt software interrupt (general purpose) device ready interrupt clock output test mode all interrupts are accessed and configured via registers arra nged into a multi-tier, branch -like structure, as shown in figure 8-1 . at the top level of the devic e interrupt structure are the interrupt status register (int_sts) , interrupt enable register (int_en) and interrupt configuration register (irq_cfg) . the interrupt status register (int_sts) and interrupt enable register (int_en) aggregate and enable/disable all inter- rupts from the various device sub-modules, combining them together to create the irq interrupt. these registers pro- vide direct interrupt access/configuration to the general purpose timer, software and device ready interrupts. these interrupts can be monitored, enabled/disabled and cleared, dire ctly within these two register s. in addition, event indica- tions are provided for the ethercat slave, power management, and ethernet phy interrupts. these interrupts differ in that the interrupt sources are generated and cleared in ot her sub-block registers. the int_sts register does not pro- vide details on what specific event wit hin the sub-module caused t he interrupt and requires the software to poll an addi- tional sub-module interrupt register (as shown in figure 8-1 ) to determine the exact interrupt source and clear it. for interrupts which involve multiple register s, only after the interrupt has been serviced and cleared at its source will it be cleared in the int_sts register. the interrupt configuration register (irq_cfg) is responsible for enabling/disabling the irq interrupt output pin as well as configuring its properties. the irq_ cfg register allows the modification of the irq pin buffer type, polarity and de-assertion interval. the de-assertion timer guarant ees a minimum interrupt de-assertion period for the irq output and is programmable via the interrupt de-assertio n interval (int_deas) field of the interrupt configuration register downloaded from: http:///
lan9252 ds00001909a-page 54 ? 2015 microchip technology inc. (irq_cfg) . a setting of all zeros disables the de-assertion timer. the de-assertion interval starts when the irq pin de- asserts, regardless of the reason. the following sections detail each category of interrupts and their related registers. refer to the corresponding functions chapter for bit-level definitions of all interrupt registers. 8.2.1 ethernet phy interrupts the ethernet phys each provide a set of id entical interrupt sources. the top-level phy a interrupt event (phy_int_a) and phy b interrupt event (phy_int_b) bits of the interrupt status register (int_sts) provide indication that a phy interrupt event occurred in the phy x interrupt source flags register (phy_interrupt_source_x) . phy interrupts are enabled/disabled via their respective phy x interrupt mask register (phy_interrupt_mask_x) . the source of a phy interrupt can be determined and cleared via the phy x interrupt source flags register (phy_in- terrupt_source_x) . unique interrupts are generated based on the following events: energyon activated auto-negotiation complete remote fault detected link down (link status negated) link up (link status asserted) auto-negotiation lp acknowledge parallel detection fault auto-negotiation page received wake-on-lan event detected figure 8-1: functional interrupt hierarchy int_cfg int_sts int_en top level interrupt registers (system csrs) phy_interrupt_source_b phy_interrupt_mask_b phy b interrupt registers bit 27 (phy_int_b) of int_sts register phy_interrupt_source_a phy_interrupt_mask_a phy a interrupt registers bit 26 (phy_int_a) of int_sts register pmt_ctrl power management control register bit 17 (pme_int) of int_sts register ecat_al_event_request ecat_al_event_mask ethercat interrupt registers bit 0 (ecat_int) of int_sts register downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 55 lan9252 in order for an interrupt event to trigger the external irq interrupt pin, the desired phy interrupt event must be enabled in the corresponding phy x interrupt mask regist er (phy_interrupt_mask_x) , the phy a interrupt event enable (phy_int_a_en) and/or phy b interrupt event enable (phy_int_b_en) bits of the interrupt enable register (int_en) must be set and the irq output must be enabled via the irq enable (irq_en) bit of the interrupt configura- tion register (irq_cfg) . for additional details on the ethernet phy interrupts, refer to section 11.2.7, "phy in terrupts," on page 128 . 8.2.2 power management interrupts multiple power management event interrupt sources are provided by the device. the top-level power management interrupt event (pme_int) bit of the interrupt status register (int_sts) provides indication that a power management interrupt event occurred in the power management control register (pmt_ctrl) . the power management control register (pmt_ctrl) provides enabling/disabling and status of all power manage- ment conditions. these include energy -detect on the phys and wake-on-lan (perfect da, broadcast, wake-up frame or magic packet) detection by phys a&b. in order for a power management interr upt event to trigger the external irq interrupt pin, the desired power manage- ment interrupt event must be enabled in the power management control register (pmt_ctrl) , the power manage- ment event interrupt enable (pme_int_en) bit of the interrupt enable register (int_en) must be set and the irq output must be enabled via the irq enable (irq_en) bit 8 of the interrupt configurati on register (irq_cfg) . the power management interrupts are only a portion of the power management features of the device. for additional details on power management, refer to section 6.3, "power management," on page 43 . 8.2.3 general purpose timer interrupt a gp timer (gpt_int) interrupt is provided in the top-level interrupt status register (int_sts) and interrupt enable register (int_en) . this interrupt is issued when the general purpose timer count register (gpt_cnt) wraps past zero to ffffh and is cleared when the gp timer (gpt_int) bit of the interrupt status register (int_sts) is written with 1. in order for a general purpose timer in terrupt event to trigger the external irq interrupt pin, the gpt must be enabled via the general purpose timer enable (timer_en) bit in the general purpose timer configuration register (gpt_cfg) , the gp timer interrupt enable (gpt_int_en) bit of the interrupt enable register (int_en) must be set and the irq output must be enabled via the irq enable (irq_en) bit of the interrupt configuration register (irq_cfg) . for additional details on the general purpose timer, refer to section 15.1, "general purpose timer," on page 297 . 8.2.4 ethercat interrupt the top-level ethercat interrupt event (ecat_int) of the interrupt status register (int_sts) provides indication that an ethercat interrupt event occurred in the al event request register . the al event mask register provides enabling/disabling of all ethercat interrupt conditions. the al event request register provides the status of all ether- cat interrupts. in order for an ethercat interrupt event to trigger the external irq interrupt pin, the desired ethercat interrupt must be enabled in the al event mask register , the ethercat interrupt event enable (ecat_int_en) bit of the interrupt enable register (int_en) must be set and the irq output must be enabled via the irq enable (irq_en) bit of the interrupt configuration register (irq_cfg) . for additional details on the ethercat interrupts, refer to section 12.0, "ethercat," on page 196 . 8.2.5 software interrupt a general purpose software interrupt is provided in the top level interrupt status register (int_sts) and interrupt enable register (int_en) . the software interrupt (sw_int) bit of the interrupt status register (int_sts) is generated when the software interrupt enable (sw_int_en) bit of the interrupt enable register (int_en) changes from cleared to set (i.e. on the rising edge of the enable). this interrupt provides an easy way for software to generate an interrupt and is designed for general software usage. in order for a software interrupt event to trigger the external irq interrupt pin, the irq output must be enabled via the irq enable (irq_en) bit of the interrupt configurati on register (irq_cfg) . downloaded from: http:///
lan9252 ds00001909a-page 56 ? 2015 microchip technology inc. 8.2.6 device ready interrupt a device ready interrupt is provided in the top-level interrupt status register (int_sts) and interrupt enable register (int_en) . the device ready (ready) bit of the interrupt status register (int_sts) indicates that the device is ready to be accessed after a power-up or reset condition. writing a 1 to this bit in the interrupt status register (int_sts) will clear it. in order for a device ready interrupt event to trigger the external irq interrupt pin, the device ready enable (ready_en) bit of the interrupt enable register (int_en) must be set and the irq output must be enabled via the irq enable (irq_en) bit of the interrupt configurati on register (irq_cfg) . 8.2.7 clock output test mode in order to facilitate system level debug, the crystal clock can be enabled onto the irq pin by setting the irq clock select (irq_clk_select) bit of the interrupt configuration register (irq_cfg) . the irq pin should be set to a push-pull driver by using the irq buffer type (irq_type) bit for the best result. 8.3 interrupt registers this section details the directly addressable interrupt rela ted system csrs. these register s control, configure and mon- itor the irq interrupt output pin and the various device interrupt sources. for an over view of the entire directly address- able register map, refer to section 5.0, "register map," on page 32 . table 0.1 interrupt registers address register name (symbol) 054h interrupt configuration register (irq_cfg) 058h interrupt status register (int_sts) 05ch interrupt enable register (int_en) downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 57 lan9252 8.3.1 interrupt configurat ion register (irq_cfg) this read/write register c onfigures and indicates the state of the irq signal. offset: 054h size: 32 bits bits description type default 31:24 interrupt de-assertion interval (int_deas) this field determines the interrupt request de-assertion interval in multiples of 10 microseconds. setting this field to zero causes the device to disable the int_deas interval, reset the interval counter and issue any pending interrupts. if a new, non-zero value is written to this field, any subsequent interrupts will obey the new set- ting. r/w 00h 23:15 reserved ro - 14 interrupt de-assertion interval clear (int_deas_clr) writing a 1 to this register clears the de-assertion counter in the interrupt controller, thus causing a new de-assertion interval to begin (regardless of whether or not the interrupt controller is currently in an active de-assertion interval). 0: normal operation 1: clear de-assertion counter r/w sc 0h 13 interrupt de-assertion status (int_deas_sts) when set, this bit indicates that the inte rrupt controller is currently in a de- assertion interval and potential interrup ts will not be sent to the irq pin. when this bit is clear, the interrupt cont roller is not currently in a de-assertion interval and interrupts will be sent to the irq pin. 0: interrupt controller not in de-assertion interval 1: interrupt controller in de-assertion interval ro 0b 12 master interrupt (irq_int) this read-only bit indicates the state of the internal irq line, regardless of the setting of the irq_en bit, or the stat e of the interrupt de-assertion function. when this bit is set, one of the enabled interrupts is currently active. 0: no enabled interrupts active 1: one or more enabled interrupts active ro 0b 11:9 reserved ro - 8 irq enable (irq_en) this bit controls the final interrupt out put to the irq pin. when clear, the irq output is disabled and permanently de-asserted. this bit has no effect on any internal interrupt status bits. 0: disable output on irq pin 1: enable output on irq pin r/w 0b 7:5 reserved ro - downloaded from: http:///
lan9252 ds00001909a-page 58 ? 2015 microchip technology inc. note 1: register bits designated as nasr are not reset when the digital_rst bit in the reset control register (reset_ctl) is set. 4 irq polarity (irq_pol) when cleared, this bit enables the irq lin e to function as an active low out- put. when set, the irq output is acti ve high. when the irq is configured as an open-drain out put (via the irq_type bit), this bit is ig nored and the inter- rupt is always active low. 0: irq active low output 1: irq active high output r/w nasr note 1 0b 3:2 reserved ro - 1 irq clock select (irq_clk_select) when this bit is set, the crystal clock ma y be output on the irq pin. this is intended to be used for system debug purposes in order to observe the clock and not for any functional purpose. note: when using this bit, the irq pin should be set to a push-pull driver. r/w 0b 0 irq buffer type (irq_type) when this bit is cleared, the irq pin functions as an open-drain output for use in a wired-or interrupt configurati on. when set, the irq is a push-pull driver. note: when configured as an open-drain output, the irq_pol bit is ignored and the interrupt output is always active low. 0: irq pin open-drain output 1: irq pin push-pull driver r/w nasr note 1 0b bits description type default downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 59 lan9252 8.3.2 interrupt status register (int_sts) this register contains the current status of the generated interrupts. a value of 1 indicates the corresponding interrupt conditions have been met, while a value of 0 indicates the inte rrupt conditions have not been met. the bits of this register reflect the status of the interrupt sour ce regardless of whether the source has been enabled as an interrupt in the inter- rupt enable register (int_en) . where indicated as r/wc, writing a 1 to the corresponding bits acknowledges and clears the interrupt. offset: 058h size: 32 bits bits description type default 31 software interrupt (sw_int) this interrupt is generated when the software interrupt enable (sw_int_en) bit of the interrupt enable register (int_en) is set high. writing a one clears this interrupt. r/wc 0b 30 device ready (ready) this interrupt indicates that the device is ready to be accessed after a power-up or reset condition. r/wc 0b 29 reserved ro - 28 reserved ro - 27 phy b interrupt event (phy_int_b) this bit indicates an interrupt event from phy b. the source of the interrupt can be determined by polling the phy x interrupt source flags register (phy_interrupt_source_x) . ro 0b 26 phy a interrupt event (phy_int_a) this bit indicates an interrupt event from phy a. the source of the interrupt can be determined by polling the phy x interrupt source flags register (phy_interrupt_source_x) . ro 0b 25:23 reserved ro - 22 reserved ro - 21:20 reserved ro - 19 gp timer (gpt_int) this interrupt is issued when the general purpose timer count register (gpt_cnt) wraps past zero to ffffh. r/wc 0b 18 reserved ro - 17 power management inte rrupt event (pme_int) this interrupt is issued when a power management event is detected as configured in the power management control register (pmt_ctrl) . writ- ing a '1' clears this bit. in order to clear this bit, all unmasked bits in the power management control register (pmt_ctrl) must first be cleared. note: the interrupt de-assertion interval does not apply to the pme interrupt. r/wc 0b 16:13 reserved ro - 12 reserved ro - downloaded from: http:///
lan9252 ds00001909a-page 60 ? 2015 microchip technology inc. 11:3 reserved ro - 2:1 reserved ro - 0 ethercat interrupt event (ecat_int) this bit indicates an ethe rcat interrupt event. the source of the interrupt can be determined by polling the al event request register . ro 0b bits description type default downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 61 lan9252 8.3.3 interrupt enable register (int_en) this register contains the interrupt enables for the irq output pin. writing 1 to any of the bits enables the corresponding interrupt as a source for irq . bits in the interrupt status register (int_sts) register will still reflect the status of the interrupt source regardless of whether the source is enabled as an interrupt in this register (with the exception of soft- ware interrupt enable (sw_int_en) . for descriptions of each interrupt, refer to the interrupt status register (int_sts) bits, which mimic the lay out of this register. offset: 05ch size: 32 bits bits description type default 31 software interrupt enable (sw_int_en) r/w 0b 30 device ready enable (ready_en) r/w 0b 29 reserved ro - 28 reserved ro - 27 phy b interrupt event enable (phy_int_b_en) r/w 0b 26 phy a interrupt event enable (phy_int_a_en) r/w 0b 25:23 reserved ro - 22 reserved ro - 21:20 reserved ro - 19 gp timer interrupt enable (gpt_int_en) r/w 0b 18 reserved ro - 17 power management event interrupt enable (pme_int_en) r/w 0b 16:13 reserved ro - 12 reserved ro - 11:3 reserved ro - 2:1 reserved ro - 0 ethercat interrupt event enable (ecat_int_en) r/w 0b downloaded from: http:///
lan9252 ds00001909a-page 62 ? 2015 microchip technology inc. 9.0 host bus interface 9.1 functional overview the host bus interface (hbi) module provides a high-spee d asynchronous slave interface that facilitates communica- tion between t he device and a host system. the hb i allows access to the system csrs and internal fifos and mem- ories and handles byte swapping based on the endianness select. the following is an overview of t he functions provided by the hbi: address bus input: two addressing modes are supported. these ar e a multiplexed address / data bus and a de- multiplexed address bus with address index register acce sses. the mode selection is done through a configura- tion input. selectable data bus width: the host data bus width is selectable. 16 and 8-bit data modes are supported. this selection is done through a configuration input. th e hbi performs byte and word to dword assembly on write data and keeps track of the byte / word count for reads. individual byte access in 16-bit mode is not supported. selectable read / write control modes: two control modes are available. separate read and write pins or an enable and direction pin. the mode selection is done through a configuration input. selectable control line polarity: the polarity of the chip select, read / write and address latch signals is select- able through configuration inputs. dynamic endianness control: the hbi supports the selection of big an d little endian host byte ordering based on the endianness signal. this highly flexible interface provides mixed endian access for registers and memory. depending on the addressing mode of the device, this signal is either configuration register controlled or as part of the strobed address input. direct fifo access: a fifo direct select signal directs all host write operations to the ethercat process ram write data fifo (multiplexed address mode only) and all host read operations from ethercat process ram read data fifo (multiplexed address mode only). this signal is strobed as part of the address input. 9.2 read / write control signals the device supports two distinct read / write signal methods: read ( rd ) and write ( wr ) strobes are input on separate pins. read and write signals are decoded from an enable input ( enb ) and a direction input ( rd_wr ). 9.3 control line polarity the device supports polarity control on the following: chip select input ( cs ) read strobe ( rd ) / direction input ( rd_wr ) write strobe ( wr ) / enable input ( enb ) address latch control ( alelo and alehi ) 9.4 multiplexed address / data mode in multiplexed address / data mode, the address, fifo direct select and endia nness select inputs are shared with the data bus. two methods are supported, a single phase addr ess, utilizing up to 16 address / data pins and a dual phase address, utilizing only the lower 8 data bits. 9.4.1 address latch cycles 9.4.1.1 single phase address latching in single phase mode, all address bits, the fifo direct sele ct signal and the endianness select are strobed into the device using the trailing edge of the alelo signal. the address latch is implemented on all 16 address / data pins. in 8-bit data mode, where pins ad[15:8] are used exclusively for addressing, it is not necessary to drive these upper address lines with a valid address continually through read an d write operations. however, this operation, referred to as partial address multiplexing, is acceptable since the device will never drive these pins. downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 63 lan9252 qualification of the alelo signal with the cs signal is selectable. when qualification is enabled, cs must be active during alelo in order to strobe the address input s. when qualification is not enabled, cs is a dont care during the address phase. the address is retained for all future read and write operations . it is retained until either a reset event occurs or a new address is loaded. this allows multiple read and write requ ests to take place to the same address, without requiring multiple address latching operations. 9.4.1.2 dual phase address latching in dual phase mode, the lower 8 address bits are strobed into the device using the inactive going edge of the alelo signal and the remaining upper address bits, the fifo direct select signals and the endianness select are strobed into the device using the trailing edge of the alehi signal. the strobes can be in eit her order. in 8-bit data mode, pins ad[15:8] are not used. in 16-bit data mode, pins d[15:8] are used only for data. qualification of the alelo and alehi signals with the cs signal is selectable. when qualification is enabled, cs must be active during alelo and alehi in order to strobe the address inpu ts. when qualification is not enabled, cs is a dont care during the address phase. the address is retained for all future read and write operations . it is retained until either a reset event occurs or a new address is loaded. this allows multiple read and write requ ests to take place to the same address, without requiring multiple address latching operations. 9.4.1.3 address bit to address / data pin mapping in 8-bit data mode, address bit 0 is multiplexed onto pin ad[0] , address bit 1 onto pin ad[1] , etc. the highest address bit is bit 9 and is multiplexed onto pin ad[9] (single phase) or ad[1] (dual phase). the address latched into the device is considered a byte address and covers 1k bytes (0 to 3ffh). in 16-bit data mode, address bit 1 is multiplexed onto pin ad[0] , address bit 2 onto pin ad[1] , etc. the highest address bit is bit 9 and is multiplexed onto pin ad[8] (single phase) or ad[0] (dual phase). the address latched into the device is considered a word address and covers 512 words (0 to 1ffh). when the address is sent to the rest of t he device, it is converted to a byte address. 9.4.1.4 endianness select to address / data pin mapping the endianness select is included into the multiplexed address to allow the host system to dynamically select the endi- anness based on the memory address used. this allows for mixed endian access for registers and memory. the endianness selection is multiplexed to the data pin one bit above the last address bit. 9.4.1.5 fifo direct select to address / data pin mapping the fifo direct select signal is included into the multip lexed address to allow the host system to address the ethercat process ram data fifos as if they were a large flat address space. the fifo direct select signal is multiplexed to the data pin two bits above the last address bit. 9.4.2 data cycles the host data bus can be 16 or 8-bits wide while all internal registers are 32 bits wide. the host bus interface performs the conversion from words or bytes to dword, while in 8 or 16-bit data mode. two or four contiguous accesses within the same dword are required in order to perform a write or read. 9.4.2.1 write cycles a write cycle occurs when cs and wr are active (or when enb is active with rd_wr indicating write). the host address and endianness were al ready captured during the address latch cycle. on the trailing edge of the write cycle (either wr or cs or enb going inactive), the host data is captured into registers in the hbi. depending on the bus width, either a word or a byt e is captured. for 8 or 16-b it data modes, this functions as the dword assembly with the affected word or byte determined by the lower address inputs. byte swapping is also done at this point based on the endianness. writes following initialization following device initialization, writes from the host bus are ignored until after a read cycle is performed. writes during and foll owing power management downloaded from: http:///
lan9252 ds00001909a-page 64 ? 2015 microchip technology inc. during and following any power management mode other than d0, writes from the host bu s are ignored until after a read cycle is performed. 8 and 16-bit access while in 8 or 16-bit data mode, the host is required to perfo rm two or four, 16 or 8-bit writes to complete a single dword transfer. no ordering requirements exist. the host can acce ss either the low or high word or byte first, as long as the other write(s) is(are) performed to the remaining word or bytes. a write byte / word counter keeps track of the number of writes. at the traili ng edge of the write cycle, the counter is incremented. once all writes occur, a 32-bit write is performed to the internal register. the write byte / word counter is reset if the power management mode is set to anything other than d0. 9.4.2.2 read cycles a read cycle occurs when cs and rd are active (or when enb is active with rd_wr indicating read). the host address and endianness were al ready captured during the address latch cycle. at the beginning of the read cycle, the app ropriate register is select ed and its data is driven onto the data pins. depend- ing on the bus width, either a word or a byte is read. fo r 8 or 16-bit data modes, the returned byte or word is determined by the endianness and the lower address inputs. polling for initialization complete before device initialization, the hbi will not return valid data. to determine when the hbi is functional, the byte order test register (byte_test) should be polled. each poll should consist of an address latch cycle(s) and a data cycle. once the correct pattern is read, the interface can be considered functional. at this point, the device ready (ready) bit in the hardware configuration register (hw_cfg) can be polled to determine when the device is fully configured. reads during and following power management during any power management mode other than d0, reads from the host bus are ignor ed. if the power management mode changes back to d0 during an active read cycle, the tail end of the read cycle is ignor ed. internal registers are not affected and the state of the hbi does not change. 8 and 16-bit access for certain register accesses, the host is required to perfor m two or four consecutive 16 or 8-bit reads to complete a single dword transfer. no ordering requirements exist. the host can access either the low or high word or byte first, as long as the other read(s) is(are) performed from the remaining word or bytes. a read byte / word counter keeps track of the number of r eads. this counter is sepa rate from the write counter above. at the trailing edge of the read cycle, the counter is incremented. on the last read for the dword, an internal read is performed to update any change on read csrs. the read byte / word counter is reset if the power management mode is set to anything other than d0. special csr handling live bits any register bit that is updated by a h/ w event is held at the beginning of th e read cycle to preven t it from changing during the read cycle. multiple byte / word live registers in 16 or 8-bit modes some registers have live fields or related fields that span across multiple bytes or words. for 16 and 8-bit data reads, it is possible for the value of these fields to ch ange between host read cycles. in order to prevent reading inter- mediate values, these registers are locked when the first byte or word is read and unlocked when the last byte or word is read. the registers are unlocked if the power managem ent mode is set to anything other than d0. note: writing the same word or bytes in the same dw ord assemble cycle may c ause undefined or unde- sirable operation. the hbi hardware does not protect against this operation. note: reading the same word or bytes from the same dword may cause undefined or undesirable opera- tion. the hbi hardware does not pr otect against this operation. the hbi simply counts that four bytes have been read. downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 65 lan9252 change on read registers and fifos fifos or change on read registers, ar e updated at the end of the read cycle. for 16 and 8-bit modes, only one internal read cycle is indicated and occurs for the last byte or word. change on read live register bits as described above, registers with live bits are held starting at the beginning of the read cycle and those that have mul- tiple bits that span across bytes or words are also locke d for 16 and 8-bit accesses. although a h/w event that occurs during the hold or lock time would still update the live bit(s), the live bit(s) will be affected (cleared, etc.) at the end of the read cycle and the h/w event would be lost. in order to prevent this, the individual csrs defer the h/w event update until after the read or multiple reads. register polling during reset or initialization some registers support polling during reset or device initializa tion to determine when the device is accessible. for these registers, only one read may be per formed without the need to read the ot her word or bytes. the same byte or word of the register may be re-read repeatedly. a register that is 16 or 8-bit readable or readable during rese t or device initialization, is not ed in its register description . 9.4.2.3 host endianness the device supports big and little endian host byte ordering based upon the endianness select that is latched during the address latch cycle. when the endianness select is low, host access is little endian and when high, host access is big endian. in a typical application the endianness select is con nected to a high-order address line, making endian selection address-based. this highly flexible interface provides mix ed endian access for registers and memory for both pio and host dma access. all internal busses are 32-bit with little endian byte orderi ng. logic within the host bus interface re-orders bytes based on the appropriate endianness bit, and the stat e of the least significant address bits. data path operations for the supported endian conf igurations and data bus sizes are illustrated in figure 9-1: little endian ordering on page 66 and figure 9-2: big endian ordering on page 67 . downloaded from: http:///
lan9252 ds00001909a-page 66 ? 2015 microchip technology inc. figure 9-1: little endian ordering 8-bit little endian 0 1 2 3 0 1 2 3 0 7 0 78 15 16 23 31 24 a = 2 a = 3 msb lsb host data bus internal order a = 0 a = 1 16-bit little endian 0 1 2 3 0 1 2 3 0 78 15 0 78 15 16 23 31 24 a = 0 a = 1 msb lsb host data bus internal order downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 67 lan9252 figure 9-2: big endian ordering 8-bit big endian 0 1 2 3 0 78 15 16 23 31 24 3 2 1 0 0 7 a = 2 a = 3 msb lsb host data bus internal order a = 1 a = 0 16-bit big endian 0 1 2 3 0 78 15 16 23 31 24 3 2 1 0 0 78 15 a = 0 a = 1 msb lsb host data bus internal order downloaded from: http:///
lan9252 ds00001909a-page 68 ? 2015 microchip technology inc. 9.4.3 ethercat process ram data fifo access 9.4.3.1 fifo direct select access a fifo direct select signal is provided allows the ho st system to address the ethercat process ram data fifos as if they were a large flat address space. when the fifo direct select signal, which was latched during the address latch cycle, is active all host write operations are to the etherc at process ram write data fifo and all host read operations are from ethercat process ram read data fifo. only the lower latched address signals are decoded in order to select the proper byte or word. all ot her address inputs are ignored in this mode. all other operations are the same (dword assembly, fifo popping, etc.). the endianness of fifo direct select accesses is determin ed by the endianness select that was latched during the address latch cycle. burst access when reading ethercat process ram read data fifo is not supported. however, since the fifo direct select signal is retained until either a reset event occurs or a new address is loaded, multiple read or write requests can occur without requiring multiple address latching operations. 9.4.4 multiplexed addr essing mode function al timing diagrams the following timing diagrams illustrate example multiplexed addressing mode read and write cycles for various address/data configurations and bus sizes. these diagrams do not cover every supported host bus permutation, but are selected to detail the main configuration differences (bus si ze, dual/single phase address latching) within the multiplexed addressing mode of operation. the following should be noted for the timing diagrams in this section: the diagrams in this section depict active-high alehi / alelo , cs , rd , and wr signals. the polarities of these signals are selectable via the hbi ale polarity , hbi chip select polarity , hbi read, read/write polarity , and hbi write, enable polarity bits of the pdi configuration register (hbi modes), respectively. refer to section 9.3, "con- trol line polarity," on page 62 for additional details. the diagrams in this section depict little endian byte or dering. however, dynamic big and little endianess are sup- ported via the endianess signal. endianess changes only th e order of the bytes involved, and not the overall tim- ing requirements. refer to section 9.4.1.4, "endianness select to address / data pin mapping," on page 63 for additional information. the diagrams in section 9.4.4.1, "dual phase address latching" and section 9.4.4.2, "single phase address latching" utilize rd and wr signals. alternative rd_wr and enb signaling is also supported, as shown in sec- tion 9.4.4.3, "rd_wr / en b control mode examples" . the hbi read/write mode is selectable via the hbi read/ write mode bit of the pdi configuration register (hbi modes). the polarities of the rd_wr and enb signals are selectable via the hbi read, read/write polarity and hbi write, enable polarity bits of the pdi configuration reg- ister (hbi modes). qualification of the alelo and/or alehi with the cs signal is selectable via the hbi ale qualification bit of the pdi configuration register (hbi modes). refer to section 9.4.1.1, "single phase address latching," on page 62 and section 9.4.1.2, "dual phase address latching," on page 63 for additional information. in dual phase address latching mode, the alehi and alelo cycles can be in any order. either or both alelo and alehi cycles maybe skipped and the device retains the last latched address. in single phase address latching mode, the alelo cycle maybe skipped and the device retains the last latched address. for 16 and 8-bit modes, consecutive address cycles mu st be within the same dwor d until the dword is com- pletely accessed (with the register exceptions noted above). although byt es and words can be accessed in any order, the diagrams in this section depi ct accessing the lower address byte or word first. note: in 8 and 16-bit modes, the alelo cycle is normally not skipped si nce sequential bytes or words are accessed in order to satisfy a comp lete dword cycle. however, there are registers for which a single byte or word access is allowed, in which case mu ltiple accesses to these registers may be performed without the need to re-latch the repeated address. downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 69 lan9252 9.4.4.1 dual phase address latching the figures in this section detail read and write operations in multiplexed addressing mode with dual phase address latching for 16 and 8-bit modes. 16-bit read the address is latched sequentially from ad[7:0] . ad[15:8] is not used or driven for the address phase. a read on ad[15:0] follows. the cycle is repeated for the other 16-bits of the dword. 16-bit read with suppressed alehi the address is latched sequentially from ad[7:0] . ad[15:8] is not used or driven for the address phase. a read on ad[15:0] follows. the lower address is th en updated to access the opposite word. figure 9-3: multiplexed addressing with dual phase latching - 16-bit read figure 9-4: multiplexed addressing with dual phase latching - 16-bit read without alehi alelo alehi cs rd wr address low address high data 15:8 data 7:0 optional address+1 low address high data 31:24 data 23:16 optional ad[15:8] ad[7:0] alelo alehi cs rd wr address low address high data 15:8 data 7:0 optional address+1 low data 31:24 data 23:16 optional ad[15:8] ad[7:0] downloaded from: http:///
lan9252 ds00001909a-page 70 ? 2015 microchip technology inc. 16-bit write the address is latched sequentially from ad[7:0] . ad[15:8] is not used or driven for the address phase. a write on ad[15:0] follows. the cycle is repeated for the other 16-bits of the dword. 16-bit write with suppressed alehi the address is latched sequentially from ad[7:0] . ad[15:8] is not used or driven for the address phase. a write on ad[15:0] follows. the lower address is th en updated to access the opposite word. figure 9-5: multiplexed addressing with dual phase latching - 16-bit write figure 9-6: multiplexed addressing with dual phase latching - 16-bit write without alehi alelo alehi cs rd wr address low address high data 15:8 data 7:0 optional address+1 low address high data 31:24 data 23:16 optional ad[15:8] ad[7:0] alelo alehi cs rd wr address low address high data 15:8 data 7:0 optional address+1 low data 31:24 data 23:16 optional ad[15:8] ad[7:0] downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 71 lan9252 16-bit reads and writes to constant address the address is latched sequentially from ad[7:0] . ad[15:8] is not used or driven for the address phase. a mix of reads and writes on ad[15:0] follows. 8-bit read the address is latched sequentially from ad[7:0] . a read on ad[7:0] follows. ad[15:8] pins are not used or driven. the cycle is repeated for the other bytes of the dword. note: generally, two 16-bit reads to oppo site words of the same dword are required, with at least the lower address changing using alelo . 16-bit reads and writes to the same word is a special case. figure 9-7: multiplexed addressing with dual phase latching - 16-bit reads and writes constant address figure 9-8: multiplexed addressing with dual phase latching - 8-bit reads alelo alehi cs rd wr address low address high data 15:8 data 7:0 optional ad[15:8] ad[7:0] data 15:8 data 7:0 data 15:8 data 7:0 data 15:8 data 7:0 data 15:8 data 7:0 ad[15:8] alelo alehi cs rd wr ad[7:0] address low address high data 7:0 optional address+1 low address high data 15:8 optional address+2 low address high data 23:16 address+3 low address high data 31:24 hi-z optional optional downloaded from: http:///
lan9252 ds00001909a-page 72 ? 2015 microchip technology inc. 8-bit read with suppressed alehi the address is latched sequentially from ad[7:0] . a read on ad[7:0] follows. ad[15:8] pins are not used or driven. the lower address is then updated to access the other bytes. 8-bit write the address is latched sequentially from ad[7:0] . a write on ad[7:0] follows. ad[15:8] pins are not used or driven. the cycle is repeated for the other bytes of the dword. figure 9-9: multiplexed addressing with dual phase latching - 8-bit reads without alehi figure 9-10: multiplexed addressing with dual phase latching - 8-bit write ad[15:8] alelo alehi cs rd wr ad[7:0] address low address high data 7:0 optional address+1 low data 15:8 optional hi-z address+2 low data 23:16 optional address+3 low data 31:24 optional alelo alehi cs rd wr address low address high data 7:0 optional address+1 low address high data 15:8 optional address+2 low address high data 23:16 address+3 low address high data 31:24 hi-z optional optional ad[15:8] ad[7:0] downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 73 lan9252 8-bit write with suppressed alehi the address is latched sequentially from ad[7:0] . a write on ad[7:0] follows. ad[15:8] pins are not used or driven. the lower address is then updated to access the other bytes. 8-bit reads and writes to constant address the address is latched sequentially from ad[7:0] . a mix of reads and writes on ad[7:0] follows. ad[15:8] pins are not used or driven. figure 9-11: multiplexed addressing with dual phase latching - 8-bit write without alehi note: generally, four 8-bit reads to oppos ite bytes of the same dword are required, with at least the lower address changing using alelo . 8-bit reads and writes to the same byte is a special case. figure 9-12: multiplexed addressing with dual phase latching - 8-bit reads and writes constant address alelo alehi cs rd wr address low address high data 7:0 optional address+1 low data 15:8 optional address+2 low data 23:16 address+3 low data 31:24 hi-z ad[15:8] ad[7:0] optional optional alelo alehi cs rd wr address low address high data 7:0 optional ad[15:8] ad[7:0] data 7:0 data 7:0 data 7:0 data 7:0 hi-z downloaded from: http:///
lan9252 ds00001909a-page 74 ? 2015 microchip technology inc. 9.4.4.2 single phase address latching the figures in this section detail multiplexed addressing mode with single phase addressing for 16 and 8-bit modes of operation. 16-bit read the address is latched simultaneously from ad[7:0] and ad[15:8] . a read on ad[15:0] follows. the cycl e is repeated for the other 16-bits of the dword. 16-bit write the address is latched simultaneously from ad[7:0] and ad[15:8] . a write on ad[15:0] follows. the cycl e is repeated for the other 16-bits of the dword. figure 9-13: multiplexed addressing with single phase latchi ng - 16-bit read figure 9-14: multiplexed addressing with single phase latching - 16-bit write alelo alehi cs rd wr address low data 15:8 data 7:0 address+1 low data 31:24 data 23:16 address high address high optional optional ad[15:8] ad[7:0] alelo alehi cs rd wr address low data 15:8 data 7:0 address+1 low data 31:24 data 23:16 address high address high optional optional ad[15:8] ad[7:0] downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 75 lan9252 16-bit reads and writes to constant address the address is latched simultaneously from ad[7:0] and ad[15:8] . a mix of reads and writes on ad[15:0] follows. 8-bit read the address is latched simultaneously from ad[7:0] and ad[15:8] . a read on ad[7:0] follows. ad[15:8] pins are not used or driven for the data phase as the host could potentially continue to drive the upper address on these signals. the cycle is repeated for the other bytes of the dword. note: generally, two 16-bit reads to oppos ite words of the same dword are required. 16-bit reads and writes to the same word is a special case. figure 9-15: multipl exed addressing with single phase latching - 16-bit reads and writes constant address figure 9-16: multiplexed addressing with single phase latching - 8-bit read alelo alehi cs rd wr address low address high data 15:8 data 7:0 optional ad[15:8] ad[7:0] data 15:8 data 7:0 data 15:8 data 7:0 data 15:8 data 7:0 data 15:8 data 7:0 alelo alehi cs rd wr address low data 7:0 address+1 low data 15:8 address high address high optional optional address+2 low data 23:16 address high address+3 low data 31:24 address high optional optional ad[15:8] ad[7:0] downloaded from: http:///
lan9252 ds00001909a-page 76 ? 2015 microchip technology inc. 8-bit write the address is latched simultaneously from ad[7:0] and ad[15:8] . a write on ad[7:0] follows. ad[15:8] pins are not used or driven for the data phase as the host could potentially continue to drive the upper address on these signals. the cycle is repeated for the other bytes of the dword. 8-bit reads and writes to constant address the address is latched simultaneously from ad[7:0] and ad[15:8] . a mix of reads and writes on ad[7:0] follows. ad[15:8] pins are not used or driven for the data phase as the ho st could potentially continue to drive the upper address on these signals. figure 9-17: multiplexed addressing with single phase latching - 8-bit write note: generally, four 8-bit reads to opposite bytes of th e same dword are required. 8-bit reads and writes to the same byte is a special case. figure 9-18: multiplexed addressing with single phase latching - 8-bit reads and writes constant address alelo alehi cs rd wr address low data 7:0 address+1 low data 15:8 address high address high optional optional address+2 low data 23:16 address high address+3 low data 31:24 address high optional optional ad[15:8] ad[7:0] alelo alehi cs rd wr address low address high data 7:0 optional ad[15:8] ad[7:0] data 7:0 data 7:0 data 7:0 data 7:0 downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 77 lan9252 9.4.4.3 rd_wr / enb control mode examples the figures in this section detail read and write operations utilizing the alternative rd_wr and enb signaling. the hbi read/write mode is selectable via the hbi read/write mode bit of the pdi configuration register (hbi modes). 16-bit note: the examples in this section detail 16-bit mode with dual phase latching. however, the rd_wr and enb signaling can be used identically in all othe r multiplexed addressing modes of operation. the examples in this section show the enb signal active-high and the rd_wr signal low for read and high for write. the polarities of the rd_wr and enb signals are selectable via the hbi read, read/write polar- ity and hbi write, enable polarity bits of the pdi configuration register (hbi modes). figure 9-19: multiplexed addressing rd_w r / enb control mode example - 16- bit read figure 9-20: multiplexed addressing rd_w r / enb control mode example - 16- bit write alelo alehi cs rd_wr enb address low address high data 15:8 data 7:0 optional address+1 low address high data 31:24 data 23:16 optional ad[15:8] ad[7:0] alelo alehi cs rd_wr enb address low address high data 15:8 data 7:0 optional address+1 low address high data 31:24 data 23:16 optional ad[15:8] ad[7:0] downloaded from: http:///
lan9252 ds00001909a-page 78 ? 2015 microchip technology inc. 9.4.5 multiplexed addressing mode timing requirements the following figures and tables specify the timing requirem ents during multiplexed address / data mode. since timing requirements are similar across the mult itude of operations (e.g. dual vs. singl e phase, 8 vs. 16-bit), many timing requirements are illustrated onto the same figures and do not necessarily repres ent any particular functional operation. the following should be noted for the timing specifications in this section: the diagrams in this section depict active-high alehi / alelo , cs , rd , wr , rd_wr and enb signals. the polarities of these signals are selectable via the hbi ale polarity , hbi chip select polarity , hbi read, read/write polarity , and hbi write, enable polarity bits of the pdi configuration register (hbi modes), respectively. refer to section 9.3, "control line polarity," on page 62 for additional details. qualification of the alelo and/or alehi with the cs signal is selectable via the hbi ale qualification bit of the pdi configuration register (hbi modes). this is shown as a dashed line. timing requirements between alelo / alehi and cs only apply when this mode is active. in dual phase address latching mode, the alehi and alelo cycles can be in any order. alehi first is depicted in solid line. alelo first is depicted in dashed line. a read cycle maybe followed by followed by an address cycle, a write cycle or another read cycle. a write cycle maybe followed by followed by a read cycle or another write cycle. these are shown in dashed line. 9.4.5.1 read timing requirements if rd and wr signaling is used, a host read cycle begins when rd is asserted with cs active. the cycle ends when rd is de-asserted. cs maybe asserted and de-asserted along with rd but not during rd active. alternatively, if rd_wr and enb signaling is used, a host read cycle begins when enb is asserted with cs active and rd_wr indicating a read. the cycle ends when enb is de-asserted. cs maybe asserted and de-asserted along with enb but not during enb active. please refer to section 9.4.4, "multiplexed addressing mode functional timing diagrams," on page 68 for functional descriptions. figure 9-21: multiplexed addressing read cycle timing alehi ad[7:0] input alelo ad[15:8] input enb, rd ad[15:8] output ad[7:0] output wr cs t adrs t adrh t csale t alerd t rddh, t csdh t aledv t rd t rddz, t csdz t aleale t wale t rdrd t rdwr t rdale t rdale t rdcyc rd_wr t rdwrs t rdwrh t csrd t rdcs t rddv, t csdv t rdon, t cson downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 79 lan9252 note 1: dual phase addressing note 2: depends on alehi / alelo order. table 9-1: multiplexed addressing read cycle timing values symbol description min typ max units t csale cs setup to alelo , alehi active note 3 , note 2 0n s t csrd cs setup to rd or enb active 0 ns t rdcs cs hold from rd or enb inactive 0 ns t wale alelo , alehi pulse width 10 ns t adrs address setup to alelo , alehi inactive 10 ns t adrh address hold from alelo , alehi inactive 5 ns t aleale alelo inactive to alehi active alehi inactive to alelo active note 1 , note 2 0n s t alerd alelo , alehi inactive to rd or enb active note 2 5n s t rdwrs rd_wr setup to enb active note 4 5n s t rdwrh rd_wr hold from enb inactive note 4 5n s t rdon rd or enb to data buffer turn on 0 ns t rddv rd or enb active to data valid 30 ns t rddh data output hold time from rd or enb inactive 0 ns t rddz data buffer turn off time from rd or enb inactive 9 ns t cson cs to data buffer turn on 0 ns t csdv cs active to data valid 30 ns t csdh data output hold time from cs inactive 0 ns t csdz data buffer turn off time from cs inactive 9 ns t aledv alelo , alehi inactive to data valid note 2 35 ns t rd rd or enb active time 32 ns t rdcyc rd or enb cycle time 45 ns t rdale rd or enb de-assertion time befo re address phase 13 ns t rdrd rd or enb de-assertion time before next rd or enb note 5 13 ns t rdwr rd de-assertion time before next wr note 5 , note 6 13 ns downloaded from: http:///
lan9252 ds00001909a-page 80 ? 2015 microchip technology inc. note 3: alelo and/or alehi qualified with the cs . note 4: rd_wr and enb signaling. note 5: no interposed address phase. note 6: rd and wr signaling. note: timing values are with respect to an equivalent test load of 25 pf. 9.4.5.2 write timing requirements if rd and wr signaling is used, a host write cycle begins when wr is asserted with cs active. the cycle ends when wr is de-asserted. cs maybe asserted and de-asserted along with wr but not during wr active. alternatively, if rd_wr and enb signaling is used, a host write cycle begins when enb is asserted with cs active and rd_wr indicating a write. the cycle ends when enb is de-asserted. cs maybe asserted and de-asserted along with enb but not during enb active. please refer to section 9.4.4, "multiplexed addressing mode functional timing diagrams," on page 68 for functional descriptions. figure 9-22: multiplexed addr essing write cycle timing alehi ad[7:0] input alelo ad[15:8] input enb, wr rd cs t adrs t adrh t csale t alewr t wr t wale t wrwr t wrrd t wrale t wrale t wrcyc rd_wr t rdwrs t rdwrh t cswr t wrcs t ds t dh t aleale downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 81 lan9252 note 7: dual phase addressing note 8: depends on alehi / alelo order. note 9: alelo and/or alehi qualified with the cs . note 10: rd_wr and enb signaling. note 11: no interposed address phase. note 12: rd and wr signaling. table 9-2: multiplexed addressing write cycle timing values symbol description min typ max units t csale cs setup to alelo , alehi active note 9 , note 8 0n s t cswr cs setup to wr or enb active 0 ns t wrcs cs hold from wr or enb inactive 0 ns t wale alelo , alehi pulse width 10 ns t adrs address setup to alelo , alehi inactive 10 ns t adrh address hold from alelo , alehi inactive 5 ns t aleale alelo inactive to alehi active alehi inactive to alelo active note 7 , note 8 0n s t alewr alelo , alehi inactive to wr or enb active note 8 5n s t rdwrs rd_wr setup to enb active note 10 5n s t rdwrh rd_wr hold from enb inactive note 10 5n s t ds data setup to wr or enb inactive 7 ns t dh data hold from wr or enb inactive 0 ns t wr wr or enb active time 32 ns t wrcyc wr or enb cycle time 45 ns t wrale wr or enb de-assertion time before address phase 13 ns t wrwr wr or enb de-assertion time before next wr or enb note 11 13 ns t wrrd wr de-assertion time before next rd note 11 , note 12 13 ns downloaded from: http:///
lan9252 ds00001909a-page 82 ? 2015 microchip technology inc. 9.5 indexed address mode in indexed address mode, access to the internal registers and memory of the device are indirectly mapped using index and data registers. the desired internal address is written into the device at a particular offset. the value written is then used as the internal address when the associate data regi ster address is accessed. three index / data register sets are provided allowing for multi-threaded operation without the concern of one thread corrupting the index set by another thread. endianness can be configured per index / data pair. another data register is provided for access to the fifos. the host address register map is given below. in 8-bit data mode, the host address input (addr[4:0]) is a byte address. in 16-bit data mode, addr0 is not provided and the host address input (addr[4:1]) is a word address. as discussed below in section 9.5.5.1, "index re gister bypass fifo access" , the ethercat process ram data fifos are accessed when reading or writing at address 18h-1bh. table 9-3: host bus interface indexed address mode register map byte address symbol register name 00h-03h hbi_idx_0 host bus interface index register 0 04h-07h hbi_data_0 host bus interface data register 0 08h-0bh hbi_idx_1 host bus in terface index register 1 0ch-0fh hbi_data_1 host bus interface data register 1 10h-13h hbi_idx_2 host bus interface index register 2 14h-17h hbi_data_2 host bus interface data register 2 18h-1bh process_ram_fifo process ram write data fifo process ram read data fifo 1ch-1fh hbi_cfg host bus inte rface configuration register downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 83 lan9252 9.5.1 host bus interf ace index register the index registers are writable as words or as bytes, depending upon the data mode. there is no concern about dword assembly rules when writing these registers. the index registers are formatted as follows: note 13: the default may be used to help determine the endianness of the register. 9.5.2 host bus interface configuration register the hbi configuration register is used to specify the endia nness of the interface. endiane ss for each index / data pair and for fifo accesses can be individually specified. the endianness of this register is irrelevant si nce each byte is shadowed into 4 positions. the hbi configuration register is writ able as words or as bytes, depending upon the data mode. there is no concern about dword assembly rules when writing this register . the configuration register is formatted as follows: bits description type default 31:16 reserved ro - 15:0 internal address the address used when the corresponding data register is accessed. note: the internal address provided by each index register is always considered to be a byte address. r/w 1234h note 13 bits description type default 31:28 reserved ro - 27 fifo endianness shadow 3 this bit is a shadow of bit 3. r/w 0b 26 host bus interface index / data register 2 endianness shadow 3 this bit is a shadow of bit 2. r/w 0b 25 host bus interface index / data register 1 endianness shadow 3 this bit is a shadow of bit 1. r/w 0b 24 host bus interface index / data register 0 endianness shadow 3 this bit is a shadow of bit 0. r/w 0b 23:20 reserved ro - 19 fifo endianness shadow 2 this bit is a shadow of bit 3. r/w 0b 18 host bus interface index / data register 2 endianness shadow 2 this bit is a shadow of bit 2. r/w 0b 17 host bus interface index / data register 1 endianness shadow 2 this bit is a shadow of bit 1. r/w 0b 16 host bus interface index / data register 0 endianness shadow 2 this bit is a shadow of bit 0. r/w 0b 15:12 reserved ro - 11 fifo endianness shadow 1 this bit is a shadow of bit 3. r/w 0b 10 host bus interface index / data register 2 endianness shadow 1 this bit is a shadow of bit 2. r/w 0b downloaded from: http:///
lan9252 ds00001909a-page 84 ? 2015 microchip technology inc. 9 host bus interface index / data register 1 endianness shadow 1 this bit is a shadow of bit 1. r/w 0b 8 host bus interface index / data register 0 endianness shadow 1 this bit is a shadow of bit 0. r/w 0b 7:4 reserved ro - 3 fifo endianness this bit specifies the endianness of fifo accesses when they are accessed by means other than the index / data register method. 0 = little endian 1 = big endian note: in order to avoid any ambiguity with the endianness of this register, bits 3, 11, 19 and 27 are shadowed. if any of these bits are set during a write, all of the bits will be set. r/w 0b 2 host bus interface index / data register 2 endianness this bit specifies the endianness of the index and data register set 2. 0 = little endian 1 = big endian note: in order to avoid any ambiguity with the endianness of this register, bits 2, 10, 18 and 26 are shadowed. if any of these bits are set during a write, all of the bits will be set. r/w 0b 1 host bus interface index / data register 1 endianness this bit specifies the endianness of the index and data register set 1. 0 = little endian 1 = big endian note: in order to avoid any ambiguity with the endianness of this register, bits 1, 9, 17 and 25 are shadowed. if any of these bits are set during a write, all of the bits will be set. r/w 0b 0 host bus interface index / data register 0 endianness this bit specifies the endianness of the index and data register set 0. 0 = little endian 1 = big endian note: in order to avoid any ambiguity with the endianness of this register, bits 0, 8, 16 and 24 are shadowed. if any of these bits are set during a write, all of the bits will be set. r/w 0b bits description type default downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 85 lan9252 9.5.3 index and configuratio n register data access the host data bus can be 16 or 8-bits wide. the hbi index registers and the hbi configuration register are 32-bits wide and are writable as words or as bytes, depending up on the data mode. they do not have nor do they require words or bytes to dword conversion. 9.5.3.1 write cycles a write cycle occurs when cs and wr are active (or when enb is active with rd_wr i ndicating write). on the trailing edge of the write cycle (eit her wr or cs or enb going inactive), the host data is capt ured into the con- figuration register or o ne for the index registers. depending on the bus width, either a word or a byte is written. the affected word or byte is determined by the endianness of the register (specified in the host bus interface configuration register ) and the lower address inputs. individual byte (in 16-bit data mode) access is not supported. writes following initialization following device initialization, writes from the host bus are ignored until after a read cycle is performed. writes during and foll owing power management during and following any power management mode other than d0, writes from the host bu s are ignored until after a read cycle is performed. 9.5.3.2 read cycles a read cycle occurs when cs and rd are active (or when enb is active with rd_wr indicating read). the host address is used directly from the host bus. at the beginning of the read cycle, the app ropriate register is select ed and its data is driven onto the data pins. depend- ing on the bus width, either a word or a byte is read. fo r 8 or 16-bit data modes, the returned byte or word is determined by the endianness of the register (specified in the host bus interface configuration register ) and the lower host address inputs. 9.5.4 internal register data access the host data bus can be 16 or 8-bits wide while all internal registers are 32 bits wide. the host bus interface performs the conversion from words or bytes to dword, while in 8 or 16-bit data mode. two or four accesses within the same dword are required in order to perform a write or read. each data register, along with the fifo direct address access, has a separate word or byte to dword conversion. accesses may be mixed among these (and the hbi index and c onfiguration register s) without concern of data corrup- tion. 9.5.4.1 write cycles a write cycle occurs when cs and wr are active (or when enb is active wi th rd_wr indicating write). the host address from the host bus selects the contents of one of the index registers. the result of this operation is captured on the leading edge of the write cycle. the host address inputs from the host bus are also captured on the leading edge of the write cycle. these are used to increment the appropriate write byte / word counter (for 8 or 16-bit data mode described below) as well as to select the correct dword a ssembly register. on the trailing edge of the write cycle (eit her wr or cs or enb going inactive), t he host data is captured into one of the data registers. depending on the bus width, either a word or a byte is captured. for 8 or 16-bit data modes, this functions as the dword assembly with the affected wo rd or byte determined by the lower host address inputs. byte swapping is also done at this point based on the endianness of the register (specified in the host bus interface configuration register ). writes following initialization following device initialization, writes from the host bus are ignored until after a read cycle is performed. note: there are separate write byte / word counters and dword assembly registers for each of the three data registers as well as for fifo access. downloaded from: http:///
lan9252 ds00001909a-page 86 ? 2015 microchip technology inc. writes during and foll owing power management during and following any power management mode other than d0, writes from the host bu s are ignored until after a read cycle is performed. 8 and 16-bit access while in 8 or 16-bit data mode, the host is required to perfo rm two or four, 16 or 8-bit writes to complete a single dword transfer. no ordering requirements exist. the host can acce ss either the low or high word or byte first, as long as the other write(s) is(are) performed to the remaining word or bytes. a write byte / word counter keeps tra ck of the number of writes. each data register has its own byte / word counter. at the trailing edge of the writ e cycle, the appropriate counter (based on the captured host address from above) is incremented. once all writes occur, a 32-bit write is performed to the inter nal register selected by the captured address from above. the data that is written is selected from on e of the three dword assembly registers based on the captured host address from above. all of the write byte / word counters are reset if the power management mode is set to anything other than d0. 9.5.4.2 read cycles a read cycle occurs when cs and rd are active (or when en b is active with rd_wr indicating read). the host address from the host bus selects the contents of one of the index regi sters. the result of this op eration is used to select the internal register to be read and also is captured on the leading edge of the read cycle. the host address inputs from the host bus are also captured on the leading edge of the read cycle. these are used to increment the appropriate read by te / word counter (for 8 or 16-bit data mode described below). at the beginning of the read cycle, the app ropriate register is select ed and its data is driven onto the data pins. depend- ing on the bus width, either a word or a byte is read. fo r 8 or 16-bit data modes, the returned byte or word is determined by the endianness of the data register (specified in the host bus interface configuration register ) and the lower host address inputs. polling for initialization complete before device initialization, the hbi will not return valid data. to determine when the hbi is functional, first the host bus interface index register 0 s hould be polled, then the byte order test re gister (byte_test) should be polled. once the correct pattern is read, the interface can be considered functional. at this point, the device ready (ready) bit in the hardware configuration register (hw_cfg) can be polled to determine when the device is fully configured. reads during and following power management during any power management mode other than d0, reads from the host bus are ignor ed. if the power management mode changes back to d0 during an active read cycle, the tail end of the read cycle is ignor ed. internal registers are not affected and the state of the hbi does not change. note: writing the same word or bytes into the same dw ord may cause undefined or undesirable operation. the hbi hardware does not protect against this operation. accessing the same internal register using two index / data register pairs may cause undefined or unde- sirable operation. the hbi hardware does not protect against this operation. mixing reads and writes into the same data register may cause undefined or un desirable operation. the hbi hardware does not prot ect against this operation. note: there are separate read byte / word counters for ea ch of the three data registers as well as for fifo access. downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 87 lan9252 8 and 16-bit access for certain register accesses, the host is required to perfor m two or four consecutive 16 or 8-bit reads to complete a single dword transfer. no ordering requirements exist. the host can access either the low or high word or byte first, as long as the other read(s) is(are) performed from the remaining word or bytes. a read byte / word counter keeps track of the number of reads. each data register has its own byte / word counter. these counters are separate from the write counters above. at the trailing edge of the read cycle, the appro- priate counter (based on the captured host address from ab ove) is incremented. on the last read for the dword, an internal read is performed to update any change on read csrs. all of the read byte / word counters are reset if the power management mode is set to anything other than d0. special csr handling live bits any register bit that is updated by a h/ w event is held at the beginning of th e read cycle to preven t it from changing during the read cycle. multiple byte / word live registers in 16 or 8-bit modes some internal registers have fields or related fields that span across multiple bytes or words. for 16 and 8-bit data reads, it is possible that the value of these fields change between host read cycl es. in order to prevent reading interme- diate values, these registers are locked when the first byte or word is read and unlocked when the last byte or word is read. the registers are unlocked if the power management mode is set to anything other than d0. change on read registers and fifos fifos or change on read registers, ar e updated at the end of the read cycle. for 16 and 8-bit modes, only one internal read cycle is indicated and occurs for the last byte or word. change on read live register bits as described above, registers with live bits are held starting at the beginning of the read cycle and those that have mul- tiple bits that span across bytes or words are also locke d for 16 and 8-bit accesses. although a h/w event that occurs during the hold or lock time would still update the live bit(s), the live bit(s) will be affected (cleared, etc.) at the end of the read cycle and the h/w event would be lost. in order to prevent this, the individual csrs defer the h/w event update until after the read or multiple reads. registers polling during reset or initialization some registers support polling during reset or device initializa tion to determine when the device is accessible. for these registers, only one read may be per formed without the need to read the ot her word or bytes. the same byte or word of the register may be re-read repeatedly. a register that is 16 or 8-bit readable or readable during rese t or device initialization, is not ed in its register description . 9.5.4.3 host endianness the device supports big and little endian host byte ordering based upon the endianness bits in the host bus interface configuration register . when the appropriate endianness bit is low, host access is little endian and when high, host access is big endian. endianness is specified for each index / data pair and for fifo direct select accesses. all internal busses are 32-bit with little endian byte orderi ng. logic within the host bus interface re-orders bytes based on the appropriate endianness bit, and the state of the least significant address lines (addr[1:0]). note: reading the same word or bytes from the same dword may cause undefined or undesirable opera- tion. the hbi hardware does not pr otect against this operation. the hbi simply counts that four bytes have been read. accessing the same internal register using two index / data register pairs may cause undefined or unde- sirable operation. the hbi hardware does not protect against this operation. mixing reads and writes into the same data regist er may cause undefined or un desirable operation. the hbi hardware does not prot ect against this operation. downloaded from: http:///
lan9252 ds00001909a-page 88 ? 2015 microchip technology inc. data path operations for the supported endian configurations and data bus sizes are illustrated in figure 9-23: little endian ordering on page 88 and figure 9-24: big endian ordering on page 89 . figure 9-23: little endian ordering 8-bit little endian 0 1 2 3 0 1 2 3 0 7 0 78 15 16 23 31 24 a = 2 a = 3 msb lsb host data bus internal order a = 0 a = 1 16-bit little endian 0 1 2 3 0 1 2 3 0 78 15 0 78 15 16 23 31 24 a = 0 a = 1 msb lsb host data bus internal order downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 89 lan9252 figure 9-24: big endian ordering 8-bit big endian 0 1 2 3 0 78 15 16 23 31 24 3 2 1 0 0 7 a = 2 a = 3 msb lsb host data bus internal order a = 1 a = 0 16-bit big endian 0 1 2 3 0 78 15 16 23 31 24 3 2 1 0 0 78 15 a = 0 a = 1 msb lsb host data bus internal order downloaded from: http:///
lan9252 ds00001909a-page 90 ? 2015 microchip technology inc. 9.5.5 ethercat process ram data fifo access 9.5.5.1 index register bypass fifo access in addition to the indexed access, th e index registers can be bypassed and th e fifos accessed at address 18h-1bh. at this address, host write operations are to the ethercat process ram writ e data fifo and host read operations are from ethercat process ram read data fifo. there is no associated index register. the endianness of fifo accesses using this method is specified by the fifo endianness bit in the host bus interface configuration register . 9.5.6 indexed address mode fu nctional timing diagrams the following timing diagrams il lustrate example indexed ( non-multiplexed) addressing mode read and write cycles for various configurations and bus sizes. these diagrams do not cover every supported ho st bus permutation, but are selected to detail the main configuration differences (bus size, configuration/index/data/f ifo-direct cycles) within the indexed addressing mode of operation. the following should be noted for the timing diagrams in this section: the diagrams in this section depict active-high cs , rd , and wr signals. the polarities of these signals are select- able via the hbi chip select polarity , hbi read, read/write polarity , and hbi write, enable polarity bits of the pdi configuration register (hbi modes), respectively. refer to section 9.3, "control line polarity," on page 62 for additional details. the diagrams in this section depict little endian byte or dering. however, configurable big and little endianess are supported via the endianness bits in the host bus interface configuration register . endianess changes only the order of the bytes involved, and not the overall timing requirements. refer to section 9.5.4.3, "host endianness," on page 87 for additional information. the diagrams in this section utilize rd and wr signals. alternative rd_wr and enb signaling is also supported, similar to the multiplexed example in section 9.4.4.3, "rd_wr / enb control mode examples" . the hbi read/ write mode is selectable via the hbi read/write mode bit of the pdi configuration register (hbi modes). the polarities of the rd_wr and enb signals are selectable via the hbi read, read/write polarity , and hbi write, enable polarity bits of the pdi configuration register (hbi modes). when accessing internal registers or fifos in 16 and 8- bit modes, consecutive address cycles must be within the same dword until the dword is comple tely accessed (some internal regist ers are excluded from this require- ment). although bytes and words can be accessed in any order, the diagrams in this section depict accessing the lower address byte or word first. 9.5.6.1 configuration register data access the figures in this section detail config uration register read and wr ite operations in indexed address mode for 16 and 8- bit modes. downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 91 lan9252 16-bit read and write for writes, the address is set to access the lower word of the configuration register. data on d[15:0] is written on the trailing edge of wr . the cycle repeats for the upper word of the co nfiguration register, if desired by the host. for reads, the address is set to access the lower word of the configuration register. read data is driven on d[15:0] during rd active. the cycle repeats for the upper word of th e configuration register, if desired by the host. 8-bit read and write for writes, the address is set to access the lowe r byte of the configuration register. data on d[7:0] is written on the trailing edge of wr . d[15:8] pins are not used or driven. the cycle repeat s for the remaining bytes of the configuration register, if desired by the host. for reads, the address is set to access the lower byte of the configuration register. read data is driven on d[7:0] during rd active. d[15:8] pins are not used or driven. the cycle repeats for the remainin g bytes of the configuration register, if desired by the host. figure 9-25: indexed addressing configurat ion register access - 16-bit write/ read figure 9-26: indexed addressing configu ration register access - 8-bit write/ read cs rd wr config,1'b0 data 15:8 d[15:8] a[4:1] config,1'b1 data 31:24 data 7:0 d[7:0] data 23:16 config,1'b0 data 15:8 data 7:0 config,1'b1 data 31:24 data 23:26 cs rd wr config,2'b00 d[15:8] a[4:0] config,2'b01 data 7:0 d[7:0] data 15:8 config,2'b00 config,2'b01 config,2'b10 config,2'b11 data 23:16 data 31:24 hi-z data 7:0 data 15:8 data 23:16 data 31:24 config,2'b10 config,2'b11 downloaded from: http:///
lan9252 ds00001909a-page 92 ? 2015 microchip technology inc. 9.5.6.2 index register data access the figures in this section detail index register read and write operations in indexed address mode for 16 and 8-bit modes. 16-bit read and write for writes, the address is set to access the lower word of one of the index registers. data on d[15:0] is written on the trailing edge of wr . the cycle repeats for the upper word of the index register, if desired by the host. for reads, the address is set to access the lower word of one of the index registers. read data is driven on d[15:0] during rd active. the cycle repeats for the upper word of the index register, if desired by the host. 8-bit read and write for writes, the address is set to access the lower byte of one of the index registers. data on d[7:0] is written on the trailing edge of wr . d[15:8] pins are not used or driven. the cycle repeat s for the remaining bytes of the index reg- ister, if desired by the host. for reads, the address is set to access the lower byte of one of the index registers. read data is driven on d[7:0] during rd active. d[15:8] pins are not used or driven. the cycle repeats for the remaining bytes of the index register, if desired by the host. note: the upper word of index registers is reserved and d ont care. therefore reads and writes to that word are not useful. figure 9-27: indexed addressing index register access - 16-bit write/read cs rd wr index,1'b0 index 15:8 d[15:8] a[4:1] index,1'b1 8'hxx index 7:0 d[7:0] 8'hxx index,1'b0 index 15:8 index 7:0 index,1'b1 8'hxx 8'hxx downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 93 lan9252 9.5.6.3 internal register data access the figures in this section detail typical internal register data read and write cycles in indexed address mode for 16 and 8-bit modes. this includes an index register write followed by either a data read or write. 16-bit read one of the index registers is set as described above. the address is then set to access the lower word of the corre- sponding data register. read data is driven on d[15:0] during rd active. the cycle repeats for the upper word of the data register. note: the upper word of index r egisters is reserved and dont care. t herefore reads and writes to those bytes are not useful. figure 9-28: indexed addressing index register access - 8-bit write/read figure 9-29: indexed addressing internal register data access - 16-bit read cs rd wr index,2'b00 d[15:8] a[4:0] index,2'b01 index 7:0 d[7:0] index 15:8 index,2'b00 index,2'b01 index,2'b10 index,2'b11 8'hxx 8'hxx hi-z index 7:0 index 15:8 8'hxx 8'hxx index,2'b10 index,2'b11 cs rd wr index,1'b0 index 15:8 d[15:8] a[4:1] index,1'b1 8'hxx index 7:0 d[7:0] 8'hxx data,1'b0 data 15:8 data 7:0 data,1'b1 data 31:24 data 23:16 downloaded from: http:///
lan9252 ds00001909a-page 94 ? 2015 microchip technology inc. 16-bit write one of the index registers is set as described above. the address is then set to access the corresponding data reg- ister. data on d[15:0] is written on the trailing edge of wr . the cycle repeats for the upper word of the data register. 16-bit reads and writes to constant internal address one of the index registers is set as descri bed above. a mix of reads and writes on d[15:0] follows, with each read or write consisting of an access to both the lower an d upper words of the corresponding data register. figure 9-30: indexed addressing internal register data access - 16-bit write figure 9-31: indexed addressing internal register data access - 16-bit reads/ writes constant address cs rd wr index,1'b0 index 15:8 d[15:8] a[4:1] index,1'b1 8'hxx index 7:0 d[7:0] 8'hxx data,1'b0 data 15:8 data 7:0 data,1'b1 data 31:24 data 23:16 cs rd wr index,1'b0 index 15:8 d[15:8] a[4:1] index,1'b1 8'hxx index 7:0 d[7:0] 8'hxx data,1'b0 data 15:8 data 7:0 data,1'b1 data 31:24 data 23:16 data,1'b0 data 15:8 data 7:0 data,1'b1 data 31:24 data 23:16 data,1'b0 data 15:8 data 7:0 data,1'b1 data 31:24 data 23:16 data,1'b0 data 15:8 data 7:0 data,1'b1 data 31:24 data 23:16 data,1'b0 data 15:8 data 7:0 data,1'b1 data 31:24 data 23:16 downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 95 lan9252 8-bit read one of the index registers is set as described above. the address is then set to access the lower byte of the corre- sponding data register. read data is driven on d[7:0] during rd active. d[15:8] pins are not used or driven. the cycle repeats for the remaining bytes of the data register. 8-bit write one of the index registers is set as described above. the address is then set to access the corresponding data reg- ister. data on d[7:0] is written on the trailing edge of wr . d[15:8] pins are not used or driven. the cycle repeats for the remaining bytes of the data register. figure 9-32: indexed addressing internal register data access - 8-bit read figure 9-33: indexed addressing internal register data access - 8-bit write cs rd wr index,2'b00 d[15:8] a[4:0] index,2'b01 index 7:0 d[7:0] index 15:8 data,2'b00 data,2'b01 index,2'b10 index,2'b11 8'hxx 8'hxx hi-z data 7:0 data 15:8 data 23:16 data 31:24 data,2'b10 data,2'b11 cs rd wr index,2'b00 d[15:8] a[4:0] index,2'b01 index 7:0 d[7:0] index 15:8 data,2'b00 data,2'b01 index,2'b10 index,2'b11 8'hxx 8'hxx hi-z data 7:0 data 15:8 data 23:16 data 31:24 data,2'b10 data,2'b11 downloaded from: http:///
lan9252 ds00001909a-page 96 ? 2015 microchip technology inc. 8-bit reads and writes to constant internal address one of the index registers is set as descr ibed above. a mix of reads and writes on d[7:0] follows, with each read or write consisting of an access to all four bytes of the corresponding data register. 9.5.6.4 rd_wr / enb control mode examples the figures in this section detail read and write operations utilizing the alternative rd_wr and enb signaling. the hbi read/write mode is selectable via the hbi read/write mode bit of the pdi configuration register (hbi modes). figure 9-34: indexed addressing internal register data access - 8-bit reads/ writes constant address note: the examples in this section detail 16-bit mode with access to an index register. however, the rd_wr and enb signaling can be used identically for all other accesses including fifo direct select access. the examples in this section show the enb signal active-high and the rd_wr signal low for read and high for write. the polarities of the rd_wr and enb signals are selectable via the hbi read, read/write polar- ity and hbi write, enable polarity bits of the pdi configuration register (hbi modes). cs rd wr index,2'b00 index 15:8 d[15:8] a[4:0] index,2'b01 index 7:0 d[7:0] data,2'b00 data 7:0 data,2'b01 data 15:8 data,2'b10 data 23:16 data,2'b00 data 7:0 data,2'b01 data 15:8 data,2'b10 data 23:16 hi-z 8'hxx index,2'b10 8'hxx index,2'b11 data,2'b10 data 23:16 data,2'b11 data 31:24 cs rd wr d[15:8] a[4:0] d[7:0] data,2'b10 data 23:16 data,2'b11 data 31:24 data,2'b00 data 7:0 data,2'b01 data 15:8 data,2'b10 data 23:16 data,2'b10 data 23:16 data,2'b11 data 31:24 downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 97 lan9252 16-bit figure 9-35: indexed addressing rd_wr / enb control mode example - 16-bit write/read cs index,1'b0 index 15:8 d[15:8] a[4:1] index,1'b1 8'hxx index 7:0 d[7:0] 8'hxx index,1'b0 index 15:8 index 7:0 index,1'b1 8'hxx 8'hxx rd_wr enb downloaded from: http:///
lan9252 ds00001909a-page 98 ? 2015 microchip technology inc. 9.5.7 indexed addressing mo de timing requirements the following figures and tables specify the timing requirements during indexed address mode. since timing require- ments are similar across the multitude of operations (e.g. 8 vs. 16-bit, index vs. configuration vs. da ta registers, fifo direct select), many timing requirements are illustrated in the same figures and do not necessarily represent any par- ticular functional operation. the following should be noted for the timing specifications in this section: the diagrams in this section depict active-high cs , rd , wr , rd_wr and enb signals. the polarities of these sig- nals are selectable via the hbi chip select polarity , hbi read, read/write polarity , and hbi write, enable polar- ity bits of the pdi configuration register (hbi modes), respectively. refer to section 9.3, "control line polarity," on page 62 for additional details. a read cycle maybe followed by followed by a write cycle or another read cycle. a write cycle maybe followed by followed by a read cycle or another write cycle. these are shown in dashed line. 9.5.7.1 read timing requirements if rd and wr signaling is used, a host read cycle begins when rd is asserted with cs active. the cycle ends when rd is de-asserted. cs maybe asserted and de-asserted along with rd but not during rd active. alternatively, if rd_wr and enb signaling is used, a host read cycle begins when enb is asserted with cs active and rd_wr indicating a read. the cycle ends when enb is de-asserted. cs maybe asserted and de-asserted along with enb but not during enb active. please refer to section 9.5.6, "indexed address mode f unctional timing diagrams," on page 90 for functional descrip- tions. figure 9-36: indexed addressing read cycle timing t rddv, t csdv a[4:0] enb, rd d[15:8] d[7:0] wr cs t rdon, t cson t rddh, t csdh t adv t rd t rddz, t csdz t rdrd t rdwr t rdcyc rd_wr t rdwrs t rdwrh t csrd t rdcs t ah t as downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 99 lan9252 note 14: rd_wr and enb signaling. note 15: rd and wr signaling. note: timing values are with respect to an equivalent test load of 25 pf. table 9-4: indexed addressing read cycle timing values symbol description min typ max units t csrd cs setup to rd or enb active 0 ns t rdcs cs hold from rd or enb inactive 0 ns t as address setup to rd or enb active 0 ns t ah address hold from to rd or enb inactive 0 ns t rdwrs rd_wr setup to enb active note 14 5n s t rdwrh rd_wr hold from enb inactive note 14 5n s t rdon rd or enb to data buffer turn on 0 ns t rddv rd or enb active to data valid 30 ns t rddh data output hold time from rd or enb inactive 0 ns t rddz data buffer turn off time from rd or enb inactive 9 ns t cson cs to data buffer turn on 0 ns t csdv cs active to data valid 30 ns t csdh data output hold time from cs inactive 0 ns t csdz data buffer turn off time from cs inactive 9 ns t adv address to data valid 30 ns t rd rd or enb active time 32 ns t rdcyc rd or enb cycle time 45 ns t rdrd rd or enb de-assertion time before next rd or enb 13 ns t rdwr rd de-assertion time before next wr note 15 13 ns downloaded from: http:///
lan9252 ds00001909a-page 100 ? 2015 microchip technology inc. 9.5.7.2 write timing requirements if rd and wr signaling is used, a host write cycle begins when wr is asserted with cs active. the cycle ends when wr is de-asserted. cs maybe asserted and de-asserted along with wr but not during wr active. alternatively, if rd_wr and enb signaling is used, a host write cycle begins when enb is asserted with cs active and rd_wr indicating a write. the cycle ends when enb is de-asserted. cs maybe asserted and de-asserted along with enb but not during enb active. please refer to section 9.5.6, "indexed address mode f unctional timing diagrams," on page 90 for functional descrip- tions. figure 9-37: indexed addressing write cycle timing table 9-5: indexed addressing write cycle timing values symbol description min typ max units t cswr cs setup to wr or enb active 0 ns t wrcs cs hold from wr or enb inactive 0 ns t as address setup to wr or enb active 0 ns t ah address hold from to wr or enb inactive 0 ns t rdwrs rd_wr setup to enb active note 16 5n s t rdwrh rd_wr hold from enb inactive note 16 5n s t ds data setup to wr or enb inactive 7 ns t dh data hold from wr or enb inactive 0 ns t wr wr or enb active time 32 ns enb, wr d[7:0] rd cs t wr t wrwr t wrrd t wrcyc rd_wr t rdwrh t cswr t wrcs t ds t dh d[15:8] a[4:0] t as t ah t rdwrs downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 101 lan9252 note 16: rd_wr and enb signaling. note 17: rd and wr signaling. t wrcyc wr or enb cycle time 45 ns t wrwr wr or enb de-assertion time before next wr or enb 13 ns t wrrd wr de-assertion time before next rd note 17 13 ns table 9-5: indexed addressing write cycle timing values (continued) symbol description min typ max units downloaded from: http:///
lan9252 ds00001909a-page 102 ? 2015 microchip technology inc. 10.0 spi/sqi slave 10.1 functional overview the spi/sqi slave module provides a lo w pin count synchronous slave interfac e that facilitates communication between the device and a host system. the spi/sqi slave allows access to the system csrs and in ternal fifos and memories. it supports single and multiple register read and write co mmands with incrementing, decr ementing and static address- ing. single, dual and quad bit lanes are supported in spi mode with a clock rate of up to 80 mhz. sqi mode always uses four bit lanes and also operates at up to 80 mhz. the following is an overview of the f unctions provided by the spi/sqi slave: serial read: 4-wire (clock, select, data in and data out) re ads at up to 30 mhz. serial command, address and data. single and multiple regist er reads with incrementing, dec rementing or static addressing. fast read: 4-wire (clock, select, data in and data out) reads at up to 80 mhz. serial command, address and data. dummy byte(s) for first access. single and multiple regist er reads with incrementing, decrementing or static addressing. dual / quad output read: 4 or 6-wire (clock, select, data in / out) re ads at up to 80 mhz. serial command and address, parallel data. dummy by te(s) for first access. single and multiple register reads with incrementing, decre- menting or static addressing. dual / quad i/o read: 4 or 6-wire (clock, select, data in / out) reads at up to 80 mhz. serial command, parallel address and data. dummy byte(s) for first access. single and multiple register reads with incrementing, decre- menting or static addressing. sqi read: 6-wire (clock, select, data in / out) writes at up to 80 mhz. parallel command, address and data. dummy byte(s) for first access. single and multiple regist er reads with incrementing, decrementing or static addressing. write: 4-wire (clock, select, data in and data out) writes at up to 80 mhz. serial co mmand, address and data. sin- gle and multiple register writes with incr ementing, decrementing or static addressing. dual / quad data write: 4 or 6-wire (clock, select, data in / out) writes at up to 80 mhz. serial command and address, parallel data. single and multiple register wr ites with incrementing, decre menting or static addressing. dual / quad address / data write: 4 or 6-wire (clock, select, data in / out) writes at up to 80 mhz. serial com- mand, parallel address and data. single and multiple regi ster writes with incrementi ng, decrementing or static addressing. sqi write: 6-wire (clock, select, data in / out) writes at up to 80 mhz. parallel command, address and data. single and multiple register writes with increm enting, decrementing or static addressing. 10.2 spi/sqi slave operation input data on the sio[3:0] pins is sampled on the rising edge of the sck input clock. output data is sourced on the sio[3:0] pins with the falling edge of the clock. the sck input clock can be either an active high pulse or an active low pulse. when the scs# chip select input is high, the sio[3:0] inputs are ignored and the sio[3:0] outputs are three- stated. in spi mode, the 8-bit instruction is started on the first rising edge of the input clock after scs# goes active. the instruc- tion is always input serially on si / sio0 . for read and write instructions, two address bytes follow the in struction byte. depending on the instruction, the address bytes are input either serially, or 2 or 4 bits per clock. although all registers are accessed as dwords, the address field is considered a byte address. fourteen address bits specify the address. bits 15 and 14 of the address field specifies that the address is auto-decremented (10b) or auto-incremented (01b) for continuous accesses. for some read instructions, dummy byte cycles follow the address bytes. the device does not drive the outputs during the dummy byte cycles. the dummy byte(s) are inpu t either serially, or 2 or 4 bits per clock. for read and write instructions, one or mo re 32-bit data fields follow the dummy bytes (if present, else they follow the address bytes). the data is input either serially, or 2 or 4 bits per clock. sqi mode is entered from spi with the enable quad i/o (eqio) instruction. once in sqi mode, all further command, addresses, dummy bytes and data bytes are 4 bits per clock. sqi mode can be exited using the reset quad i/o (rstqio) instruction. downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 103 lan9252 all instructions, addresses and data are transferred with the mo st-significant bit (msb) or di-bit (msd) or nibble (msn) first. addresses are transferred with the most-significant byte (msb) first. data is transferred with the least-significant byte (lsb) first (little endian). the spi interface supports up to a 80 mhz input clock. norma l (non-high speed) reads inst ructions are limited to 30 mhz. the spi interface supports a minimum time of 50 ns between successive commands (a minimum scs# inactive time of 50 ns). the instructions supported in spi mode are listed in table 10-1 . sqi instructions are listed in table 10-2 . unsupported instructions are must not be used. note 1: the bit width format is: command bit width, address / dummy bit width, data bit width. table 10-1: spi instructions instruction description bit width note 1 inst. code addr. bytes dummy bytes data bytes max freq. configuration eqio enable sqi 1-0-0 38h 0 0 0 80 mhz rstqio reset sqi 1-0-0 ffh 0 0 0 80 mhz read read read 1-1-1 03h 2 0 4 to ? 30 mhz fastread read at higher speed 1-1-1 0bh 2 1 4 to ? 80 mhz sdor spi dual output read 1-1-2 3bh 2 1 4 to ? 80 mhz sdior spi dual i/o read 1-2-2 bbh 2 2 4 to ? 80 mhz sqor spi quad out- put read 1-1-4 6bh 2 1 4 to ? 80 mhz sqior spi quad i/o read 1-4-4 ebh 2 4 4 to ? 80 mhz write write write 1-1-1 02h 2 0 4 to ? 80 mhz sddw spi dual data write 1-1-2 32h 2 0 4 to ? 80 mhz sdadw spi dual address / data write 1-2-2 b2h 2 0 4 to ? 80 mhz sqdw spi quad data write 1-1-4 62h 2 0 4 to ? 80 mhz sqadw spi quad address / data write 1-4-4 e2h 2 0 4 to ? 80 mhz downloaded from: http:///
lan9252 ds00001909a-page 104 ? 2015 microchip technology inc. note 2: the bit width format is: command bit width, address / dummy bit width, data bit width. 10.2.1 device initialization until the device has been initialized to the point where the various configuration inputs are valid, the spi/sqi interface does not respond to and is not affected by any external pin activity. once device initialization completes, the spi/sqi interface will ignore the pins until a rising edge of scs# is detected. 10.2.1.1 spi/sqi slave read po lling for initialization complete before device initialization, the spi/sqi interface will not return valid data. to determine when the spi/sqi interface is functional, the byte order test register (byte_test) should be polled. once the corre ct pattern is read, the interface can be considered functional. at this point, the device ready (ready) bit in the hardware configuration register (hw_cfg) can be polled to determine when the device is fully configured. 10.2.2 access during and following power management during any power management mode other than d0, reads an d writes are ignored and t he spi/sqi interface does not respond to and is not affected by any external pin activity. once the power management mode changes back to d0, the sp i/sqi interface will ignore the pins until a rising edge of scs# is detected. to determine when the spi/sqi interface is functional, the byte order test register (byte_test) should be polled. once the correct pattern is read, the interface can be considered functional. at this point, the device ready (ready) bit in the hardware configuration register (hw_cfg) can be polled to determine when the device is fully configured. 10.2.3 spi configuration commands 10.2.3.1 enable sqi the enable sqi instruction changes the mode of op eration to sqi. this instruction is supported in spi bus protocol only with clock frequencies up to 80 mhz . this instruction is not su pported in sqi bus protocol. the spi slave interface is selected by first bringing scs# active. the 8-bit eqio instruction, 38h , is input into the si / sio[0] pin one bit per clock. the scs# input is brought inacti ve to conclude the cycle. table 10-2: sqi instructions instruction description bit width note 2 inst. code addr. bytes dummy bytes data bytes max freq. configuration rstqio reset sqi 4-0-0 ffh 0 0 0 80 mhz read fastread read at higher speed 4-4-4 0bh 2 3 4 to ? 80 mhz write write write 4-4-4 02h 2 0 4 to ? 80 mhz note: the host should only use single register reads (one data cycle per scs# low) while polling the byte_test register. note: the host should only use single register reads (one data cycle per scs# low) while polling the byte_test register. downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 105 lan9252 figure 10-1 illustrates the en able sqi instruction. 10.2.3.2 reset sqi the reset sqi instruction changes the mode of operation to spi. this instruction is supported in spi and sqi bus pro- tocols with clock frequencies up to 80 mhz . the spi/sqi slave interface is selected by first bringing scs# active. the 8-bit rstqio instruction, ffh , is input into the si / sio[0] pin, one bit per clock, in spi mode and into the sio[3:0] pins, four bits per clock, in sqi mode. the scs# input is brought inactive to conclude the cycle. figure 10-2 illustrates the reset sqi instruction for spi mode. figure 10-3 illustrates the reset sqi instruction for sqi mode. figure 10-1: enable sqi figure 10-2: spi mode reset sqi spi enable sqi sck (active high) si 0011 0 x instruction 0 so 10 z sck (active low) scs# x 1 2 3 4 5 6 7 8 x 1 2 3 4 5 6 7 8 x x x spi mode reset sqi sck (active high) si 1111 1 x instruction 1 so 11 z sck (active low) scs# x 1 2 3 4 5 6 7 8 x 1 2 3 4 5 6 7 8 x x x downloaded from: http:///
lan9252 ds00001909a-page 106 ? 2015 microchip technology inc. 10.2.4 spi read commands various read commands are support by the spi/sqi slave. the following applies to all read commands. multiple reads additional reads, beyond the first, are perfo rmed by continuing the clock pulses while scs# is active. the upper two bits of the address specify auto-increment ing (address[15:14]=01b) or auto-decre menting (address[15:14]=10b). the inter- nal dword address is incremented, decremented, or mainta ined based on these bits. maintaining a fixed internal address is useful for register polling. special csr handling live bits since data is read serially, the selected registers value is saved at the beginning of each 32-bit read to prevent the host from reading an intermediate value. the saving o ccurs multiple times in a multiple read sequence. change on read registers and fifos any register that is affected by a read operation (e.g. a clear on read bit or fifo) is updated once the current data output shift has started. in the event th at 32-bits are not read when the scs# is returned high, the regi ster is still affected and any prior data is lost. change on read live register bits as described above, the current value from a register with live bits (as is the case of any register) is saved before the data is shifted out. although a h/w event t hat occurs following the data capture woul d still update the live bit(s), the live bit(s) will be affected (cleared, etc.) once the output shift has started and the h/w event would be lost. in order to prevent this, the individual csrs defer the h/w ev ent update until after the read indication. 10.2.4.1 read the read instruction inputs the instruction code and address bytes one bit per clock and outputs the data one bit per clock. this instruction is sup ported in spi bus protocol only with clock frequencies up to 30 mhz . this instruction is not supported in sqi bus protocol. the spi slave interface is selected by first bringing scs# active. the 8-bit read instruction, 03h , is input into the si / sio[0] pin, followed by the two address bytes. the addr ess bytes specify a byte address within the device. on the falling clock edge following the rising edge of the last address bit, the so / sio[1] pin is driven starting with the msb of the lsb of the selected regist er. the remaining register bits are shifted out on subsequent falling clock edges. the scs# input is brought inactive to conclude the cycle. the so / sio[1] pin is three-stated at this time. figure 10-3: sqi mode reset sqi sqi mode reset sqi sck (active high) sio[3:0] ff x sck (active low) scs# x 1 2 x 1 2 x x x inst downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 107 lan9252 figure 10-4 illustrates a typical single and multiple register read. 10.2.4.2 fast read the read at higher speed instruction inputs the instruction code and the address and dummy bytes one bit per clock and outputs the data one bit per clock. in sqi mode, t he instruction code and the address and dummy bytes are input four bits per clock and the data is output four bits per clo ck. this instruction is supported in spi and sqi bus protocols with clock frequencies up to 80 mhz . the spi/sqi slave interface is selected by first bringing scs# active. for spi mode, the 8-bit fastread instruction, 0bh , is input into the si / sio[0] pin, followed by the two address bytes and 1 dummy byte. for sqi mode, the 8-bit fas- tread instruction is input into the sio[3:0] pins, followed by the two address bytes and 3 dummy bytes. the address bytes specify a byte address within the device. on the falling clock edge following the rising edge of the last dummy bit (or nibble), the so / sio[1] pin is driven starting with the msb of the lsb of the selected register. for sqi mode, sio[3:0] are driven starting with the msn of the lsb of the selected register. the remaining register bits are shifted out on subsequent falling clock edges. the scs# input is brought inactive to conclude the cycle. the so / sio[3:0] pins are three-stated at this time. figure 10-4: spi read spi read single register sck (active high) si 0000 1 x instruction 1 address x so de c data a 13 ... ... x ... spi read multiple registers 00 d 7 d 6 d 5 z z x sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 53 54 55 56 x x 53 54 55 56 d 26 d 24 in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 sck (active high) si 0000 1 x instruction 1 address x so de c a 13 ... x ... 00 z sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 x x in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 ... d 7 d 6 d 5 d 26 d 24 ... d 7 d 6 d 5 d 26 d 24 z x x ... ... d 25 d 25 d 25 data 1... data m data m+1... data n ... downloaded from: http:///
lan9252 ds00001909a-page 108 ? 2015 microchip technology inc. figure 10-5 illustrates a typical single and multip le register fast read for spi mode. figure 10-6 illustrates a typical single and multiple register fast read for sqi mode. figure 10-5: spi fast read figure 10-6: sqi fast read spi fast read single register sck (active high) si 0000 1 x instruction 1 address x so de c data a 13 ... ... x ... spi fast read multiple registers 10 d 7 d 6 d 5 z z x sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 33 34 35 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 33 34 35 61 62 63 64 x x 61 62 63 64 d 26 d 24 in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 sck (active high) si x instruction address x so de c a 13 ... x ... z sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 ... d 7 d 6 d 5 d 26 d 24 ... d 7 d 6 d 5 d 26 d 24 z x x ... ... x x x x x x x x 25 26 27 28 29 30 31 32 25 26 27 28 29 30 31 32 dummy x x x x x x x x dummy 25 26 27 28 29 30 31 25 26 27 28 29 30 31 32 32 33 34 35 33 34 35 0000 1 1 10 d 25 d 25 d 25 data 1... data m data m+1... data n ... sqi fast read single register sck (active high) sio[3:0] x inst address h1 data h 0 sqi fast read multiple registers h 0 l0 h 1 x sck (active low) scs# x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x l2 l3 l1 l0 17 18 19 20 17 18 19 20 sck (active high) x ... sck (active low) scs# ... x x x x ... ... x ... data 1... data m data n x x x x x x dummy sio[3:0] 0 b l1 h 2 h 3 inst address h1 h 0 h 0 l0 h 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 l1 l0 x x x x x x dummy 0 b 15 data m+1... l2 l3 h 3 h 0 l0 h 1 l2 l3 h 3 ... downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 109 lan9252 10.2.4.3 dual output read the spi dual output read instruction inputs the instruction code and the address and dummy bytes one bit per clock and outputs the data two bits per clock. this instruction is supported in spi bus protocol only with clock frequencies up to 80 mhz . this instruction is not su pported in sqi bus protocol. the spi slave interface is selected by first bringing scs# active. the 8-bit sdor instruction, 3bh , is input into the sio[0] pin, followed by the two address bytes and 1 dummy byte. the address bytes specify a byte address within the device. on the falling clock edge following the rising edge of the last dummy di-bit, the sio[1:0] pins are driven starting with the msbs of the lsb of the selected register. the remaining regist er di-bits are shifted out on subsequent falling clock edges. the scs# input is brought inactive to conclude the cycle. the sio[1:0] pins are three-stated at this time. figure 10-7 illustrates a typical single and mu ltiple register dual output read. figure 10-7: spi dual output read spi dual output read single register sck (active high) sio0 0011 1 x instruction 1 address sio1 de c data a 13 ... ...... spi dual output read multiple registers 10 d 7 d 6 d 5 z z x sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 33 34 35 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 33 34 35 45 46 47 48 x x 45 46 47 48 d 29 in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 sck (active high) sio0 x instruction address sio1 de c a 13 ...... z sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 ... ... ... ... x x x x x x x x 25 26 27 28 29 30 31 32 25 26 27 28 29 30 31 32 dummy x x x x x x x x dummy 25 26 27 28 29 30 31 25 26 27 28 29 30 31 32 32 33 34 35 33 34 35 0011 1 1 10 d 25 data 1... data m data m+1... data n ... d 4 d 3 d 2 d 24 d 28 d 26 d 27 x data d 7 d 6 d 5 d 4 d 3 d 2 d 29 d 25 d 24 d 28 d 26 d 27 d 7 d 6 d 5 d 4 d 3 d 2 z x d 29 d 25 d 24 d 28 d 26 d 27 x data 1... data m data m+1... data n downloaded from: http:///
lan9252 ds00001909a-page 110 ? 2015 microchip technology inc. 10.2.5 quad output read the spi quad output read instruction inputs the instruction code and the address and dummy bytes one bit per clock and outputs the data four bits per clock. this instruction is supported in spi bus protocol only with clock frequencies up to 80 mhz . this instruction is not su pported in sqi bus protocol. the spi slave interface is selected by first bringing scs# active. the 8-bit sqor instruction, 6bh , is input into the sio[0] pin, followed by the two address bytes and 1 dummy byte. the address bytes specify a byte address within the device. on the falling clock edge following the rising edge of the last dummy bit, the sio[3:0] pins are driven starting with the msn of the lsb of the selected register. the remaining register nibbles are shifted out. the scs# input is brought inactive to conclude the cycle. the sio[3:0] pins are three-stated at this time. figure 10-8 illustrates a typical single and mu ltiple register quad output read. figure 10-8: spi quad output read spi quad output read single register sck (active high) sio0 011 1 x instruction 1 address sio1 de c data a 13 spi quad output read multiple registers 10 d 5 d 4 d 1 z z x sck (active low) scs# x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 33 34 35 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 33 34 35 37 38 39 40 x x 37 38 39 40 d 17 in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 sck (active high) sio0 x instruction address sio1 de c a 13 ...... z sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 ... ... ... ... x x x x x x x x 25 26 27 28 29 30 31 32 25 26 27 28 29 30 31 32 dummy x x x x x x x x dummy 25 26 27 28 29 30 31 25 26 27 28 29 30 31 32 32 33 34 35 33 34 35 d 25 data 1... data m data m+1... data n ... d 0 d 13 d 12 d 24 d 16 d 28 d 29 x data d 5 d 4 d 1 d 0 d 13 d 12 d 17 d 25 d 24 d 16 d 28 d 29 z x x data 1... data m data m+1... data n sio2 z ... ... data 1... data m data m+1... data n d 6 d 2 d 14 d 18 d 26 d 30 z x sio3 z ... ... data 1... data m data m+1... data n d 7 d 3 d 15 d 19 d 27 d 31 z x d 5 d 4 d 1 d 0 d 13 d 12 d 6 d 2 d 14 d 7 d 3 d 15 d 17 d 25 d 24 d 16 d 28 d 29 d 18 d 26 d 30 d 19 d 27 d 31 sio2 z d 6 d 2 d 14 d 18 d 26 d 30 sio3 z d 7 d 3 d 15 d 19 d 27 d 31 z x z x 0 011 1 1 10 0 data data 36 36 d 9 d 8 d 21 d 20 d 10 d 22 d 11 d 23 downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 111 lan9252 10.2.5.1 dual i/o read the spi dual i/o read instruction inputs the instruction code one bi t per clock and the address and dummy bytes two bits per clock and outputs the data two bits per clock. this instruction is supported in spi bus protocol only with clock frequencies up to 80 mhz . this instruction is not supported in sqi bus protocol. the spi slave interface is selected by first bringing scs# active. the 8-bit sdior instruction, bbh , is input into the sio[0] pin, followed by the two address bytes and 2 dummy bytes into the sio[1:0] pins. the address bytes specify a byte address within the device. on the falling clock edge following the rising edge of the last dummy di-bit, the sio[1:0] pins are driven starting with the msbs of the lsb of the selected register. the remaining regist er di-bits are shifted out on subsequent falling clock edges. the scs# input is brought inactive to conclude the cycle. the sio[1:0] pins are three-stated at this time. figure 10-9 illustrates a typical single and mu ltiple register dual i/o read. figure 10-9: spi dual i/o read spi dual i/o read single register sck (active high) sio0 1 x instruction 1 address sio1 de c data a 13 ... ...... spi dual i/o read multiple registers 10 d 7 d 6 d 5 z z x sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 37 38 39 40 x x 37 38 39 40 d 29 in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 sck (active high) sio0 x instruction sio1 ...... sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 ... ... ... ... x x x x x x x x 25 26 27 25 26 27 dummy x 25 26 27 25 26 27 d 25 data 1... data m data m+1... data n ... d 4 d 3 d 2 d 24 d 28 d 26 d 27 x data d 7 d 6 d 5 d 4 d 3 d 2 d 29 d 25 d 24 d 28 d 26 d 27 d 7 d 6 d 5 d 4 d 3 d 2 z x d 29 d 25 d 24 d 28 d 26 d 27 x data 1... data m data m+1... data n x x x x x x x x 11 10 11 10 11 10 address de c a 13 in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 z x x x x x x x x dummy x x x x x x x address dummy address dummy downloaded from: http:///
lan9252 ds00001909a-page 112 ? 2015 microchip technology inc. 10.2.5.2 quad i/o read the spi quad i/o read instruction inputs the instruction code one bit per clock and the address and dummy bytes four bits per clock and outputs the data four bits per clock. this instruction is supported in spi bus protocol only with clock frequencies up to 80 mhz . this instruction is not supported in sqi bus protocol. the spi slave interface is selected by first bringing scs# active. the 8-bit sqior instruction, ebh , is input into the sio[0] pin, followed by the two address bytes and 4 dummy bytes into the sio[3:0] pins. the address bytes specify a byte address within the device. on the falling clock edge following the ri sing edge of the last dummy nibble, the sio[3:0] pins are driven starting with the msn of the lsb of the se lected register. the remaining register nibble s are shifted out on subsequent falling clock edges. the scs# input is brought inactive to conclude the cycle. the sio[3:0] pins are three-stated at this time. figure 10-10 illustrates a typical single and multiple register quad i/o read. figure 10-10: spi quad i/o read spi quad i/o read single register sck (active high) sio0 111 1 x instruction 1 sio1 data spi quad i/o read multiple registers 10 d 5 d 4 d 1 z x sck (active low) scs# x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 28 x x 25 26 27 28 d 17 17 18 19 20 21 22 23 17 18 19 20 21 22 23 sck (active high) sio0 x instruction address sio1 de c a 13 ...... z sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 17 18 19 20 21 22 23 17 18 19 20 21 22 23 ... ... ... ... x x x x x x x x dummy d 25 data 1... data m data m+1... data n ... d 0 d 13 d 12 d 24 d 16 d 28 d 29 x data d 5 d 4 d 1 d 0 d 13 d 12 d 17 d 25 d 24 d 16 d 28 d 29 z x x data 1... data m data m+1... data n sio2 z ... ... data 1... data m data m+1... data n d 6 d 2 d 14 d 18 d 26 d 30 z x sio3 z ... ... data 1... data m data m+1... data n d 7 d 3 d 15 d 19 d 27 d 31 z x d 5 d 4 d 1 d 0 d 13 d 12 d 6 d 2 d 14 d 7 d 3 d 15 d 17 d 25 d 24 d 16 d 28 d 29 d 18 d 26 d 30 d 19 d 27 d 31 sio2 d 6 d 2 d 14 d 18 d 26 d 30 sio3 d 7 d 3 d 15 d 19 d 27 d 31 z x z x 0 111 1 1 10 0 x x x x x x x x dummy x x x x x x x x dummy x x x x x x x x dummy address de c a 13 z in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 z z x x x x x x x x dummy x x x x x x x x dummy x x x x x x x x dummy x x x x x x x x dummy 24 24 d 9 d 8 d 21 d 20 d 10 d 22 d 11 d 23 downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 113 lan9252 10.2.6 spi write commands multiple write commands are support by the spi/sqi slave. the following applies to all write commands. multiple writes multiple reads are performed by continuing the clock pulses and input data while scs# is active. the upper two bits of the address specify auto-incrementing (a ddress[15:14]=01b) or auto-decrementing (address[15:14]=10b). the internal dword address is increment ed, decremented, or maintained based on these bits. maintaining a fixed internal address may be useful for register bit-b anging or other repeated writes. 10.2.6.1 write the write instruction inputs the instruction code and address and data bytes one bit per clock. in sqi mode, the instruc- tion code and the address and data bytes are input four bits per clock. this instruction is supported in spi and sqi bus protocols with clock frequencies up to 80 mhz . the spi/sqi slave interface is selected by first bringing scs# active. for spi mode, the 8-bit write instruction, 02h , is input into the si / sio[0] pin, followed by the two address bytes. for sqi mode, the 8-bit write instruction, 02h , is input into the sio[3:0] pins, followed by the two address bytes. the address bytes specify a byte address within the device. the data follows the address bytes. for spi mode, the data is input into the si / sio[0] pin starting with the msb of the lsb. for sqi mode the data is input nibble wide using sio[3:0] starting with the msn of the lsb. the remaining bits/ nibbles are shifted in on subsequent clock edges. the data write to the register occurs after the 32-bits are input. in the event that 32-bits are not written when the scs# is returned high, the write is cons idered invalid and the register is not affected. the scs# input is brought inactive to conclude the cycle. figure 10-11 illustrates a typical single and multiple register write for spi mode. figure 10-12 illustrates a typical single and multiple register write for sqi mode. figure 10-11: spi write spi write single register sck (active high) si 0000 x instruction 1 address so de c data a 13 ... ... spi write multiple registers 00 d 7 d 6 d 5 z x sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 53 54 55 56 x x 53 54 55 56 d 26 d 24 in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 sck (active high) si 0000 x instruction address so de c a 13 ... 00 z sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 x x in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 ... d 7 d 6 d 5 d 26 d 24 ... d 7 d 6 d 5 d 26 d 24 x ... d 25 d 25 d 25 data 1... data m data m+1... data n ... 0 1 0 downloaded from: http:///
lan9252 ds00001909a-page 114 ? 2015 microchip technology inc. figure 10-12: sqi write sqi write single register sck (active high) sio[3:0] x inst address h1 data h 0 sqi write multiple registers h 0 l0 h 1 x sck (active low) scs# x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 x x l2 l3 l1 l0 sck (active high) x ... sck (active low) scs# ... x x x x ... ... x ... data 1... data m data n sio[3:0] 0 2 l1 h 2 h 3 inst address h1 h 0 h 0 l0 h 1 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 l1 l0 0 2 data m+1... l2 l3 h 3 h 0 l0 h 1 l2 l3 h 3 ... downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 115 lan9252 10.2.6.2 dual data write the spi dual data write instruction inputs the instruction code and address bytes one bit per clock and inputs the data two bits per clock. this instruction is supported in spi bus protocol only with clock frequencies up to 80 mhz . this instruction is not supported in sqi bus protocol. the spi slave interface is selected by first bringing scs# active. the 8-bit sddw instruction, 32h , is input into the sio[0] pin, followed by the two address bytes. the address bytes specify a byte address within the device. the data follows the address bytes. the data is input into the sio[1:0] pins starting with the msbs of the lsb. the remaining di-bits are shifted in on subsequent clock edges. the data write to the register occurs after the 32-bits are input. in the event that 32-bi ts are not written when the scs# is returned high, the write is considered invalid and the register is not affected. the scs# input is brought inactive to conclude the cycle. figure 10-13 illustrates a typical single and multiple register dual data write. figure 10-13: spi dual data write spi dual data write single register sck (active high) sio0 0011 x instruction 1 address sio1 de c data a 13 ... ... spi dual data write multiple registers 00 z x sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 37 38 39 40 x x 37 38 39 40 in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 sck (active high) sio0 x instruction address sio1 de c a 13 ... z sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 x x in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 ... ... ... data 1... data m data m+1... data n ... 0 1 0 data ... d 7 d 6 d 5 z x d 29 d 25 d 4 d 3 d 2 d 24 d 28 d 26 d 27 x 0011 00 ... ... data 1... data m data m+1... data n d 7 d 5 d 3 d 29 d 25 d 27 d 7 d 5 d 3 z x d 29 d 25 d 27 d 6 d 4 d 2 d 24 d 28 d 26 d 6 d 4 d 2 d 24 d 28 d 26 x downloaded from: http:///
lan9252 ds00001909a-page 116 ? 2015 microchip technology inc. 10.2.6.3 quad data write the spi quad data write instruction inputs the instruction code and address bytes one bit per clock and inputs the data four bits per clock. this instruct ion is supported in spi bus protocol only with clock frequencies up to 80 mhz . this instruction is not supported in sqi bus protocol. the spi slave interface is selected by first bringing scs# active. the 8-bit sqdw instruction, 62h , is input into the sio[0] pin, followed by the two address bytes. the address bytes specify a byte address within the device. the data follows the address bytes. the data is input into the sio[3:0] pins starting with the msn of the lsb. the remain- ing nibbles are shifted in on subsequent clock edges. the data write to the register occurs after the 32-bits are input. in the event that 32-bits ar e not written when the scs# is returned high, the write is considered invalid and the register is not affected. the scs# input is brought inactive to conclude the cycle. figure 10-14 illustrates a typical single and multiple register quad data write. figure 10-14: spi quad data write spi quad data write single register sck (active high) sio0 00 11 x instruction 1 address sio1 de c a 13 spi quad data write multiple registers 00 z sck (active low) scs# x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 x x in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 sck (active high) sio0 x instruction address sio1 de c a 13 ... z sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 x x in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 ... ... 0 data d 5 d 4 d 1 z x d 17 d 25 d 0 d 13 d 12 d 24 d 16 d 28 d 29 x data d 6 d 2 d 14 d 18 d 26 d 30 d 7 d 3 d 15 d 19 d 27 d 31 z x z x data data d 9 d 8 d 21 d 20 d 10 d 22 d 11 d 23 sio2 z sio3 z 28 29 30 31 32 28 29 30 31 32 ... ... ... ... data 1... data m data m+1... data n d 5 d 4 d 1 d 0 d 13 d 12 d 17 d 25 d 24 d 16 d 28 d 29 z x x data 1... data m data m+1... data n ... ... data 1... data m data m+1... data n d 6 d 2 d 14 d 18 d 26 d 30 z x ... ... data 1... data m data m+1... data n d 7 d 3 d 15 d 19 d 27 d 31 z x d 5 d 4 d 1 d 0 d 13 d 12 d 6 d 2 d 14 d 7 d 3 d 15 d 17 d 25 d 24 d 16 d 28 d 29 d 18 d 26 d 30 d 19 d 27 d 31 sio2 z sio3 z 00 11 1 00 0 downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 117 lan9252 10.2.6.4 dual address / data write the spi dual address / data write instruction inputs the instruction code one bit per clock and the address and data bytes two bits per clock. this instruction is support ed in spi bus protocol only with clock frequencies up to 80 mhz . this instruction is not supported in sqi bus protocol. the spi slave interface is selected by first bringing scs# active. the 8-bit sdadw instruction, b2h , is input into the sio[0] pin, followed by the two address bytes into the sio[1:0] pins. the address bytes specify a byte address within the device. the data follows the address bytes. the data is input into the sio[1:0] pins starting with the msbs of the lsb. the remaining di-bits are shifted in on subsequent clock edges. the data write to the register occurs after the 32-bits are input. in the event that 32-bi ts are not written when the scs# is returned high, the write is considered invalid and the register is not affected. the scs# input is brought inactive to conclude the cycle. figure 10-15 illustrates a typical single and multiple register dual address / data write. figure 10-15: spi dual address / data write spi dual address / data write single register sck (active high) sio0 011 x instruction 1 sio1 data ... ... spi dual address / data write multiple registers 00 z x sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 29 30 31 32 x x 29 30 31 32 17 18 19 17 18 19 sck (active high) sio0 x instruction sio1 ... sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x 17 18 19 17 18 19 ... ... ... data 1... data m data m+1... data n ... 0 data ... d 7 d 6 d 5 z x d 29 d 25 d 4 d 3 d 2 d 24 d 28 d 26 d 27 x ... ... data 1... data m data m+1... data n d 7 d 5 d 3 d 29 d 25 d 27 d 7 d 5 d 3 z x d 29 d 25 d 27 d 6 d 4 d 2 d 24 d 28 d 26 d 6 d 4 d 2 d 24 d 28 d 26 x 1 address de c a 13 in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 address z address de c a 13 in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 address 011 1 00 0 1 downloaded from: http:///
lan9252 ds00001909a-page 118 ? 2015 microchip technology inc. 10.2.6.5 quad address / data write the spi quad address / data write instruction inputs the instruction code one bit per clock and the address and data bytes four bits per clock. this instruction is suppor ted in spi bus protocol only with clock frequencies up to 80 mhz . this instruction is not supported in sqi bus protocol. the spi slave interface is selected by first bringing scs# active. the 8-bit sqadw instruction, e2h , is input into the sio[0] pin, followed by the two address bytes into the sio[3:0] pins. the address bytes specify a byte address within the device. the data follows the address bytes. the data is input into the sio[3:0] pins starting with the msn of the lsb. the remain- ing nibbles are shifted in on subsequent clock edges. the data write to the register occurs after the 32-bits are input. in the event that 32-bits ar e not written when the scs# is returned high, the write is considered invalid and the register is not affected. the scs# input is brought inactive to conclude the cycle. figure 10-16 illustrates a typical single and multiple register dual address / data write. figure 10-16: spi qu ad address / data write spi quad address / data write single register sck (active high) sio0 0 11 x instruction 1 sio1 spi quad address / data write multiple registers 00 sck (active low) scs# x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x 17 18 19 20 17 18 19 20 sck (active high) sio0 x instruction sio1 ... sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 x x ... ... 0 data d 5 d 4 d 1 z x d 17 d 25 d 0 d 13 d 12 d 24 d 16 d 28 d 29 x data d 6 d 2 d 14 d 18 d 26 d 30 d 7 d 3 d 15 d 19 d 27 d 31 z x z x data data d 9 d 8 d 21 d 20 d 10 d 22 d 11 d 23 sio2 sio3 ... ... ... ... data 1... data m data m+1... data n d 5 d 4 d 1 d 0 d 13 d 12 d 17 d 25 d 24 d 16 d 28 d 29 z x x data 1... data m data m+1... data n ... ... data 1... data m data m+1... data n d 6 d 2 d 14 d 18 d 26 d 30 z x ... ... data 1... data m data m+1... data n d 7 d 3 d 15 d 19 d 27 d 31 z x d 5 d 4 d 1 d 0 d 13 d 12 d 6 d 2 d 14 d 7 d 3 d 15 d 17 d 25 d 24 d 16 d 28 d 29 d 18 d 26 d 30 d 19 d 27 d 31 sio2 sio3 0 11 1 00 0 address de c a 13 z in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 z z address de c a 13 in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 z z z 11 downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 119 lan9252 10.3 spi/sqi timing requirements note 3: the read instruction is limi ted to 30 mhz maximum note 4: depends on loading of 30 pf or 10 pf note 5: depending on the clock frequency and pulse width, data may not be valid until following the next rising edge of sck . the host spi controller may need to delay the sampling of the data by either a fixed time or by using the falling edge of sck . figure 10-17: spi/sqi input timing figure 10-18: spi/sqi output timing table 10-3: spi/sqi timing values symbol description min typ max units f sck sck clock frequency note 3 30 / 80 mhz t high sck high time 5.5 ns t low sck low time 5.5 ns t scss scs# setup time to sck 5n s t scsh scs# hold time from sck 5n s t scshl scs# inactive time 50 ns t su data input setup time to sck 3n s t hd data input hold time from sck 4n s t on data output turn on time from sck 0n s t v data output valid time from sck note 4 , note 5 11.0/9.0 ns t ho data output hold time from sck 0n s t dis data output disable time from scs# inactive 20 ns sck si/sio[3:0] scs# t scss t high t low t su t hd t scshl t scsh so/sio[3:0] sck t high t low scs# t dis t on t v t ho downloaded from: http:///
lan9252 ds00001909a-page 120 ? 2015 microchip technology inc. 11.0 ethernet phys 11.1 functional overview the device contains phys a and b. the a and b phys are identical in functi onality. phy a connects to the ethercat core port 0 or 2. phy b connects to ethercat core port 1. these phys interface with their respective mac via an internal mii interface. the phys comply with the ieee 802.3 physical layer for tw isted pair ethernet and can be configured for full duplex 100 mbps (100base-tx / 100base-fx) ethe rnet operation. all phy registers follow the ieee 802. 3 (clause 22.2.4) specified mii management register set and are fully configurable. 11.1.1 phy addressing the address for phy a is set to 0 or 2, based on the device mode, and the address for phy b is fixed to 1. in addition, the addresses for phy a and b can be changed via the phy address (phyadd) field in the phy x special modes register (phy_special_modes_x) . for proper operation, the addresses for phys a and b must be unique. no check is performed to assure each phy is set to a different address. 11.2 phys a & b the device integrates two ieee 802.3 phy functions. the phys can be configured for either 100 mbps copper (100base-tx) or 100 mbps fiber (100base-fx) ethernet operation and include auto-negotiation and hp auto-mdix. 11.2.1 functional description functionally, each phy can be divided into the following sections: 100base-tx transmit and 100base-tx receive auto-negotiation hp auto-mdix phy management control and phy interrupts phy power-down modes wake on lan (wol) resets link integrity test cable diagnostics loopback operation 100base-fx far end fault indication note: because phys a and b are functionally identical, this section will describe them as the phy x, or simply phy. wherever a lowercase x has been appended to a port or signal name, it can be replaced with a or b to indicate the phy a or phy b respectively. in some instances, a 1 or a 2 may be appropriate instead. all references to phy in this section can be used interchangeably for both the phys a and b. downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 121 lan9252 a block diagram of the main components of each phy can be seen in figure 11-1 . 11.2.2 100base-tx transmit the 100base-tx transmit data path is shown in figure 11-2 . shaded blocks are those which are internal to the phy. each major block is explained in the following sections. 11.2.2.1 100base-tx transmit data ac ross the internal mii interface for a transmission, the ethercat core ma c drives the transmit data onto the internal mii txd bus and asserts the inter- nal mii txen to indicate valid data. the data is in the form of 4-bit wide 25 mhz data. figure 11-1: phy block diagram figure 11-2: 100base-tx transmit data path hp auto-mdix txpx/txnx rxpx/rxnx to external port x ethernet pins 100 transmitter 100 reciever mii mac interface mii mdio auto- negotiation to port x ethercat mac to ethercat core pll phy management control registers from system clocks controller interrupts to system interrupt controller port x mac 100m tx driver mlt-3 converter nrzi converter 4b/5b encoder magnetics cat-5 rj45 100m pll internal mii 25 mhz by 4 bits internal mii transmit clock 25mhz by 5 bits nrzi mlt-3 mlt-3 mlt-3 mlt-3 scrambler and piso 125 mbps serial mii mac interface 25mhz by 4 bits downloaded from: http:///
lan9252 ds00001909a-page 122 ? 2015 microchip technology inc. 11.2.2.2 4b/5b encoder the transmit data passes from the mii block to the 4b/5b enc oder. this block encodes the data from 4-bit nibbles to 5- bit symbols (known as code-groups) according to ta b l e 11 - 1 . each 4-bit data-nibble is mapped to 16 of the 32 possible code-groups. the remaining 16 code-groups are either used for control information or are not valid. the first 16 code-groups are referred to by the hexadecimal values of their corresponding data nibbles, 0 through f. the remaining code-groups are given letter designations with slashe s on either side. for example, an idle code-group is / i/, a transmit error code-group is /h/, etc. table 11-1: 4b/5b code table code group sym receiver interpreta tion transmitter interpretation 11110 0 0 0000 data 0 0000 data 01001 1 1 0001 1 0001 10100 2 2 0010 2 0010 10101 3 3 0011 3 0011 01010 4 4 0100 4 0100 01011 5 5 0101 5 0101 01110 6 6 0110 6 0110 01111 7 7 0111 7 0111 10010 8 8 1000 8 1000 10011 9 9 1001 9 1001 10110 a a 1010 a 1010 10111 b b 1011 b 1011 11010 c c 1100 c 1100 11011 d d 1101 d 1101 11100 e e 1110 e 1110 11101 f f 1111 f 1111 11111 /i/ idle sent after /t/r/ until the mii transmitter enable signal (txen) is received 11000 /j/ first nibble of ssd, translated to 0101 following idle, else mii receive error (rxer) sent for rising mii transmitter enable signal (txen) 10001 /k/ second nibble of ssd, translated to 0101 following j, el se mii receive error (rxer) sent for rising mii transmitter enable signal (txen) 01101 /t/ first nibble of esd, causes de-assertion of crs if followed by /r/, else assertion of mii receive error (rxer) sent for falling mii transmitter enable signal (txen) 00111 /r/ second nibble of esd, causes de-asser- tion of crs if following /t/, else assertion of mii receive error (rxer) sent for falling mii transmitter enable signal (txen) 00100 /h/ transmit error symbol sent fo r rising mii transmit error (txer) downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 123 lan9252 11.2.2.3 scrambler and piso repeated data patterns (especially the idle code-group) ca n have power spectral densities with large narrow-band peaks. scrambling the data helps eliminate these peaks and spread the signal power more uniformly over the entire channel bandwidth. this uniform spectral density is required by fcc regulations to prevent excessive emi from being radiated by the physical wiring. the seed for the scrambler is generated from the phy addr ess, ensuring that each phy will have its own scrambler sequence. for more information on phy addressing, refer to section 11.1.1, "phy addressing" . the scrambler also performs the parallel in serial out conversion (piso) of the data. 11.2.2.4 nrzi and mlt-3 encoding the scrambler block passes the 5-bit wide parallel data to t he nrzi converter where it becomes a serial 125mhz nrzi data stream. the nrzi is then encoded to mlt-3. mlt-3 is a tri-level code where a change in the logic level represents a code bit 1 and the logic output remaining at the same level represents a code bit 0. 11.2.2.5 100m transmit driver the mlt-3 data is then passed to the analog transmitter, which drives the differential mlt-3 signal on output pins txpx and txnx, to the twisted pair media across a 1:1 ratio is olation transformer. the transmitter drives into the 100 ? imped- ance of the cat-5 cable. cable termination and impedance matching require external components. 11.2.2.6 100m phase lock loop (pll) the 100m pll locks onto the reference clock and generates the 125 mhz clock used to drive the 125 mhz logic and the 100base-tx transmitter. 00110 /v/ invalid, mii re ceive error (rxer) if during mii receive data valid (rxdv) invalid 11001 /v/ invalid, mii re ceive error (rxer) if during mii receive data valid (rxdv) invalid 00000 /p/ invalid invalid 00001 /v/ invalid, mii receive error (rxer) if during mii receive data valid (rxdv) invalid 00010 /v/ invalid, mii receive error (rxer) if during mii receive data valid (rxdv) invalid 00011 /v/ invalid, mii re ceive error (rxer) if during mii receive data valid (rxdv) invalid 00101 /v/ invalid, mii receive error (rxer) if during mii receive data valid (rxdv) invalid 01000 /v/ invalid, mii receive error (rxer) if during mii receive data valid (rxdv) invalid 01100 /v/ invalid, mii re ceive error (rxer) if during mii receive data valid (rxdv) invalid 10000 /v/ invalid, mii receive error (rxer) if during mii receive data valid (rxdv) invalid table 11-1: 4b/5b code table (continued) code group sym receiver interpreta tion transmitter interpretation downloaded from: http:///
lan9252 ds00001909a-page 124 ? 2015 microchip technology inc. 11.2.3 100base-tx receive the 100base-tx receive data path is shown in figure 11-3 . shaded blocks are those which are internal to the phy. each major block is explained in the following sections. 11.2.3.1 100m receive input the mlt-3 data from the cable is fed into the phy on inputs rxpx and rxnx via a 1:1 ratio transformer. the adc sam- ples the incoming differential signal at a rate of 125m sa mples per second. using a 64-level quantizer, 6 digital bits are generated to represent each sample. the dsp adjusts the gain of the adc according to the observed signal levels such that the full dynamic range of the adc can be used. 11.2.3.2 equalizer, blw correcti on and clock/data recovery the 6 bits from the adc are fed into the dsp block. the equ alizer in the dsp section compensates for phase and ampli- tude distortion caused by the physical channel consisting of magnetics, connectors, and cat- 5 cable. the equalizer can restore the signal for any good-qua lity cat-5 cable between 1m and 100m. if the dc content of t he signal is such that the low-frequency comp onents fall below the low frequency pole of the iso- lation transformer, then the droop characteristics of the transformer will become significant and baseline wander (blw) on the received signal will result. to prevent corruption of the received data, the phy corrects for blw and can receive the ansi x3.263-1995 fddi tp-pmd defined killer packet with no bit errors. the 100m pll generates multiple phases of the 125mhz clock. a multip lexer, controlled by the timing unit of the dsp, selects the optimum phase for sampling the data. this is used as the received recovered clock. this clock is used to extract the serial data from the received signal. 11.2.3.3 nrzi and mlt-3 decoding the dsp generates the mlt-3 recovered le vels that are fed to the mlt-3 converter. the mlt-3 is then converted to an nrzi data stream. 11.2.3.4 descrambler the descrambler performs an inverse function to the scrambler in the transmitter and also performs the serial in parallel out (sipo) conversion of the data. figure 11-3: 100base-tx receive data path port x mac a/d converter mlt-3 converter nrzi converter 4b/5b decoder magnetics cat-5 rj45 100m pll internal mii 25mhz by 4 bits internal mii receive clock 25mhz by 5 bits nrzi mlt-3 mlt-3 mlt-3 6 bit data descrambler and sipo 125 mbps serial dsp: timing recovery, equalizer and blw correction mlt-3 mii mac interface 25mhz by 4 bits downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 125 lan9252 during reception of idle (/i/) symbols. the descrambler synchronizes its descram bler key to the incoming stream. once synchronization is achieved, the descrambler locks on this key and is able to descramble incoming data. special logic in the descrambler ensures synchronization wi th the remote transceiver by searching for idle symbols within a window of 4000 bytes (40 us). this window ensures that a maximum packet size of 1514 bytes, allowed by the ieee 802.3 standard, can be received wi th no interference. if no idle-symbols are detected within this time-period, receive operation is aborted and the descram bler re-starts the synchronization process. the de-scrambled signal is then aligned into 5-bit code-grou ps by recognizing the /j/k/ st art-of-stream delimiter (ssd) pair at the start of a packet. once the code-word alignment is determined, it is stored and utilized until the next start of frame. 11.2.3.5 5b/4b decoding the 5-bit code-groups are translated into 4-bit data nibbles according to the 4b/5b table. the translated data is pre- sented on the internal mii rxd[3:0] signal lines. the ssd, /j/k/, is translated to 0101 0101 as the first 2 nibbles of the mac preamble. reception of the ssd causes the transceiver to assert the receive data valid signal, indicating that valid data is available on the rxd bus. successive valid code-groups are translated to data nibbles. reception of either the end of stream delimiter (esd) consisting of the /t/r/ symbols , or at least two /i/ symbols causes the transceiver to de- assert carrier sense and receive data valid signal. 11.2.3.6 receive data valid signal the internal miis receive data valid signal (rxdv) indicates that recovered and decoded nibbles are being presented on the rxd[3:0] outputs synchronous to rxclk. rxdv becom es active after the /j/k/ delimiter has been recognized and rxd is aligned to nibble boundaries. it remains active until either the /t/r/ delimiter is recognized or link test indi- cates failure or sigdet becomes false. rxdv is asserted when the first nibble of translated /j/k/ is ready for trans fer over the media independent interface. 11.2.3.7 receiver errors during a frame, unexpected code-groups are considered re ceive errors. expected code groups are the data set (0 through f), and the /t/r/ (esd) symbol pair. when a receive error occurs, the internal miis rxer signal is asserted and arbitrary data is driven onto the internal miis rxd[3:0] lines. should an error be detected during the time that the / j/k/ delimiter is being decoded (bad ssd error), rxer is as serted true and the value 11 10b is driven onto the rxd[3:0] lines. note that the internal miis data valid signal (rxdv) is not yet assert ed when the bad ssd occurs. 11.2.3.8 100m receive data acro ss the internal mii interface for reception, the 4-bit data nibbles are sent to the mii ma c interface block. these data nibbles are clocked to the con- troller at a rate of 25 mhz. rxclk is the output clock for the internal mii bus. it is recovered from the received data to clock the rxd bus. if there is no received signal, it is derived from the system reference clock. 11.2.4 auto-negotiation the purpose of the auto-negotiation func tion is to automatically configure the transceiver to the optimum link parame- ters based on the capabilities of its link partner. auto-nego tiation is a mechanism for exchanging configuration informa- tion between two link-partners and automatically selectin g the highest performance mode of operation supported by both sides. auto-negotiation is fully defined in clause 28 of the ieee 802.3 spec ification and is enabled by setting the auto-negotiation enable (phy_an) of the phy x basic control regist er (phy_basic_control_x) . the advertised capabilities of the phy are stored in the phy x auto-negotiation advert isement register (phy_an_ad- v_x) . the phy contains the ability to advertise 100base-tx and 10base-t in both full or half-duplex modes. besides the connection speed, the phy can advertise remote fault i ndication and symmetric or asymmetric pause flow control as defined in the ieee 802.3 specification. the transceiver supports next page capability which is used to negotiate energy efficient ethernet functionality as well as to sup port software controlled pages. many of the default advertised capabilities of the phy are determined via configuration straps as shown in section 11.2.16.5, "p hy x auto-negotiation advertisement register (phy_an_adv_x)," on page 150 . refer to section 7.0, "configuration straps," on page 51 for additional details on how to use the device configuration straps. note: these symbols are not translated into data. note: auto-negotiation is not used for 100base-fx mode. downloaded from: http:///
lan9252 ds00001909a-page 126 ? 2015 microchip technology inc. once auto-negotiation has completed, information about the resolved link and the results of the negotiation process are reflected in the speed indication bits in the phy x special control/status register (phy_special_con- trol_status_x) , as well as the phy x auto-negotiation link partner base page ability register (phy_an_lp_base_ability_x) . the auto-negotiation protocol is a purely physical layer activity and proceeds inde- pendently of the mac controller. the following blocks are activated during an auto-negotiation session: auto-negotiation (digital) 100m adc (analog) 100m pll (analog) 100m equalizer/blw/clock recovery (dsp) 10m squelch (analog) 10m pll (analog) 10m transmitter (analog) when enabled, auto-negotiation is started by the occurrence of any of the following events: power-on reset (por) hardware reset (rst#) phy software reset (via reset control register (reset_ctl) , or bit 15 of the phy x basic control register (phy_basic_control_x) ) phy power-down reset ( section 11.2.8, "phy power-down modes," on page 131 ) phy link status down (bit 2 of the phy x basic status register (phy_basic_status_x) is cleared) setting the phy x basic control register (phy_basic_control_x) , bit 9 high (auto-neg restart) ethercat system reset on detection of one of these ev ents, the transceiver begins auto-negotiation by transmitting bursts of fast link pulses (flp). these are bursts of link pulses from the 10m tx driver. they are s haped as normal link pulses and can pass uncorrupted down cat-3 or cat-5 cable. a fast link pulse burst consists of up to 33 pulses. the 17 odd-numbered pulses, which are always present, fram e the flp burst. the 16 even-numbered pu lses, which may be present or absent, contain the data word being transmitted. presence of a dat a pulse represents a 1, while absence represents a 0. the data transmitted by an flp burst is known as a link code word. these are defined fully in ieee 802.3 clause 28. in summary, the transceiver advertises 802.3 compliance in its selector field (the first 5 bits of the link code word). it advertises its technology ability according to the bits set in the phy x auto-negotiation advertisement register (phy_an_adv_x) . there are 4 possible matches of the technology abilities. in the order of priority these are: 100m full duplex (highest priority) 100m half duplex 10m full duplex 10m half duplex (lowest priority) if the full capabilities of the transceiver are advertised (100m, full-duplex), and if the link partner is capable of 10m and 100m, then auto-negotiation selects 100m as the highest pe rformance mode. if the link partner is capable of half and full-duplex modes, then auto-negotiation sele cts full-duplex as the highest performance mode. once a capability match has been determined, the link code words are repeated with the acknowledge bit set. any dif- ference in the main content of the link code words at this time will caus e auto-negotiation to re-start. auto-negotiation will also re-start if not all of the required flp bursts are received. writing the phy x auto-negotiation advertisement register (phy_an_adv_x) bits [8:5] allows software control of the capabilities advertised by the transceiver. writing the phy x auto-negotiation advertisement register (phy_an_ad- v_x) does not automatically re-start auto-negotiation. the restart auto-negotiation (phy_rst_an) bit of the phy x basic control register (phy_basic_control_x) must be set before the new abilities will be advertised. auto-nego- tiation can also be disabled via software by clearing the auto-negotiation enable (phy_an) bit of the phy x basic con- trol register (phy_basic_control_x) . note: refer to section 6.2, "resets," on page 38 for information on these and other system resets. downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 127 lan9252 11.2.4.1 parallel detection if the device is connected to a device lack ing the ability to auto-negotiate (i.e. no flps are detected), it is able to deter- mine the speed of the link based on either 100m mlt-3 symbols or 10m normal link pulses. in this case the link is presumed to be half-duplex per the ieee 802.3 standard. this ability is known as paralle l detection. this feature ensures interoperability with legacy link partners. if a link is formed via parallel detection, then the link partner auto- negotiation able bit of the phy x auto-negotiation exp ansion register (phy_an_exp_x) is cleared to indicate that the link partner is not capable of auto-negotiation. if a fault occurs during parallel detection, the parallel detection fault bit of the phy x auto-negotiation expansion register (phy_an_exp_x) is set. the phy x auto-negotiation link pa rtner base page ability regi ster (phy_an_lp_base_ability_x) is used to store the link partner ability information, which is coded in the re ceived flps. if the link partner is not auto-negotiation capa- ble, then this register is updated after completion of parallel detection to reflect the speed capability of the link partner. 11.2.4.2 restarting auto-negotiation auto-negotiation can be re-started at any time by setting the restart auto-negotiation (phy_rst_an) bit of the phy x basic control register (phy_basic_control_x) . auto-negotiation will also re-start if the link is broken at any time. a broken link is caused by signal loss. this may occur because of a cable break, or because of an interruption in the signal transmitted by the link partner. auto-negotiation re sumes in an attempt to determine the new link configuration. if the management entity re-starts auto-negotiation by setting the restart auto-negotiation (phy_rst_an) bit of the phy x basic control regist er (phy_basic_control_x) , the device will respond by stopping all transmission/receiv- ing operations. once the internal break_link_time is comp leted in the auto-negotiation state-machine (approximately 1200ms), auto-negotiation will re-start. in this case, the li nk partner will have also dropped the link due to lack of a received signal, so it too will resume auto-negotiation. 11.2.4.3 disabling auto-negotiation auto-negotiation can be disabled by clearing the auto-negotiation enable (phy_an) bit of the phy x basic control register (phy_ basic_control_x) . the transceiver will then force its speed of operation to reflect the information in the phy x basic control register (phy_basic_control_x) ( speed select lsb (phy_speed_sel_lsb) and duplex mode (phy_duplex) ). these bits are ignored when auto-negotiation is enabled. 11.2.4.4 half vs. full-duplex half-duplex operation relies on the csma /cd (carrier sense multiple access / collision detect) protocol to handle net- work traffic and collisions. in this mode , the carrier sense signal, crs, responds to both transmit and receive activity. if data is received while the transceiver is transmitting, a collision results. in full-duplex mode, the transceiver is able to transmit and receive data simultaneously. in this mode, crs responds only to receive activity. the csma/cd protocol does not apply and collision detection is disabled. 11.2.5 hp auto-mdix hp auto-mdix facilitates the use of cat-3 (10 base-t) or cat-5 (100 base-t) media utp interconnect cable without consideration of interface wiring scheme. if a user plugs in either a direct connect lan cable or a cross-over patch cable, as shown in figure 11-4 , the transceiver is capable of configuring the txpx/txnx and rxpx/rxnx twisted pair pins for correct transceiver operation. the internal logic of the device detects the tx and rx pi ns of the connecting device. si nce the rx and tx line pairs are interchangeable, special pcb design considerations are needed to accommodate the symmetrical magnetics and termination of an auto-mdix design. software based control of the auto-mdi x function may be performed using the auto-mdix control (amdixctrl) bit of the phy x special control/status indication register (phy _special_control_stat_ind_x) . when amdixctrl is set to 1, the auto-mdix capability is determined by the auto-mdix enable (amdixen) and auto-mdix state (amdix- state) bits of the phy x special control/status indication register (phy_special_control_stat_ind_x) . note: auto-mdix is not used for 100base-fx mode. downloaded from: http:///
lan9252 ds00001909a-page 128 ? 2015 microchip technology inc. 11.2.6 phy management control the phy management control block is responsible for the m anagement functions of the phy, including register access and interrupt generation. a serial manag ement interface (smi) is used to support registers as required by the ieee 802.3 (clause 22), as well as the vendor specific registers allowed by the specif ication. the smi in terface consists of the mii management data (mdio) signal and the mii manag ement clock (mdc) signal. these signals allow access to all phy registers. refer to section 11.2.16, "phy registers," on page 142 for a list of all supported registers and register descriptions. non-supported r egisters will be read as ffffh. 11.2.7 phy interrupts the phy contains the ability to generate various interrupt events. reading the phy x interrupt source flags register (phy_interrupt_source_x) shows the source of the interrupt. the phy x interrupt mask re gister (phy_inter- rupt_mask_x) enables or disables each phy interrupt. the phy management control block aggregates the enabled inte rrupts status into an internal signal which is sent to the system interrupt controlle r and is reflected via the phy a interrupt event (phy_int_a) and phy b interrupt event (phy_int_b) bits of the interrupt status r egister (int_sts) . for more information on t he device interrupts, refer to section 8.0, "system interrupts," on page 53 . the phy interrupt system provides two modes, a primary interrupt mode and an alternative interrupt mode. both modes will assert the internal interrupt signal sent to the system interrupt controller when the corresponding mask bit is set. these modes differ only in how they de-assert the internal interrupt signal. these modes are detailed in the following subsections. note: when operating in 10base-t or 100base-tx manual modes, the auto -mdix crossover time can be extended via the extend manual 10/100 auto-mdix crossover time bit of the phy x edpd nlp / cross- over time / eee configurati on register (phy_edpd_cfg_x) . refer to section 11.2.16.12, on page 159 for additional information. when energy detect power-down is enabled, the au to-mdix crossover time can be extended via the edpd extend crossover bit of the phy x edpd nlp / crossover ti me / eee configuration register (phy_edpd_cfg_x) . refer to section 11.2.16.12, on page 159 for additional information figure 11-4: direct cable connection vs. cross-over cable connection note: the primary interrupt mode is the default interrupt mode after a power-up or hard reset. the alternative interrupt mode requires setup after a power-up or hard reset. 12 3 4 5 6 7 8 txpx txnx rxpx not used not used rxnx not used not used 12 3 4 5 6 7 8 txpx txnx rxpx not used not used rxnx not used not used direct connect cable rj-45 8-pin straight-through for 10base-t/100base-tx signaling 12 3 4 5 6 7 8 txpx txnx rxpx not used not used rxnx not used not used 12 3 4 5 6 7 8 txpx txnx rxpx not used not used rxnx not used not used cross-over cable rj-45 8-pin cross-over for 10base-t/100base-tx signaling downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 129 lan9252 11.2.7.1 primary interrupt mode the primary interrupt mode is the default interrupt mode. th e primary interrupt mode is always selected after power-up or hard reset. in this mode, to enable an interrupt, set the corresponding mask bit in the phy x interrupt mask register (phy_interrupt_mask_x) (see table 11-2 ). when the event to assert an interrupt is true, the internal interrupt sig- nal will be asserted. when the correspondin g event to de-assert the interrupt is tr ue, the internal interrupt signal will be de-asserted. note 1: linkstat is the internal link status and is not directly available in any register bit. note 2: wol_int is defined as bits 7:4 in the phy x wakeup control and status register (phy_wucsr_x) anded with bits 3:0 of the same register, wi th the resultant 4 bits ored together. table 11-2: interrupt management table mask interrupt source flag interrupt source event to assert interrupt event to de-assert interrupt 30.9 29.9 link up linkstat see note 1 link status rising link- stat falling linksat or reading register 29 30.8 29.8 wake on lan wol_int see note 2 enabled wol event rising wol_int falling wol_int or reading register 29 30.7 29.7 energyon 17.1 energyon rising 17.1 ( note 3 ) falling 17.1 or reading register 29 30.6 29.6 auto-negotia- tion complete 1.5 auto-negoti- ate com- plete rising 1.5 falling 1.5 or reading register 29 30.5 29.5 remote fault detected 1.4 remote fault rising 1.4 falling 1.4, or reading register 1 or reading register 29 30.4 29.4 link down 1.2 link status falling 1.2 reading register 1 or reading register 29 30.3 29.3 auto-negotia- tion lp acknowl- edge 5.14 acknowl- edge rising 5.14 falling 5.14 or reading register 29 30.2 29.2 parallel detec- tion fault 6.4 parallel detection fault rising 6.4 falling 6.4 or reading register 6, or reading register 29, or re-auto negotiate or link down 30.1 29.1 auto-negotia- tion page received 6.1 page received rising 6.1 falling 6.1 or reading register 6, or reading register 29, or re-auto negotiate, or link down. downloaded from: http:///
lan9252 ds00001909a-page 130 ? 2015 microchip technology inc. note 3: if the mask bit is enabled and the internal interrupt signal has been de-asserted while energyon is still high, the internal interrupt signal will assert for 256 ms, approximately one second after energyon goes low when the cable is unplugged. to prevent an unexpected assertion of the internal interrupt signal, the energyon interrupt mask should always be cleared as part of the energyon interrupt service routine. 11.2.7.2 alternat e interrupt mode the alternate interrupt mode is enabled by setting the altint bit of the phy x mode control/status register (phy_- mode_control_status_x) to 1. in this mode, to enable an interrupt, set the corresponding bit of the in the phy x interrupt mask register (phy_interrupt_mask_x) (see ta b l e 11 - 3 ). to clear an interru pt, clear the interrupt source and write a 1 to the corresponding interrupt source flag. writing a 1 to the interrupt source flag will cause the state machine to check the interrupt source to determine if the interrupt source flag should clear or stay as a 1. if the condition to de-assert is true, then t he interrupt source flag is cleared and the internal interrupt signal is also deas- serted. if the condition to de-assert is false, then the interrupt source flag rema ins set, and the internal interrupt signal remains asserted. note 4: linkstat is the internal link status and is not directly available in any register bit. note: the energy on (energyon) bit in the phy x mode control/status register (phy_mode_con- trol_status_x) is defaulted to a 1 at the start of th e signal acquisition process, therefore the int7 bit in the phy x interrupt source flags register (phy_interrupt_source_x) will also read as a 1 at power-up. if no signal is present, then both energy on (energyon) and int7 will clear within a few mil- liseconds. table 11-3: alternative interrupt mode management table mask interrupt source flag interrupt source event to assert interrupt condition to de-assert bit to clear interrupt 30.9 29.9 link up linkstat see note 4 link status rising link- stat linkstat low 29.9 30.8 29.8 wake on lan wol_int see note 5 enabled wol event rising wol_int wol_int low 29.8 30.7 29.7 energyon 17.1 energyon rising 17.1 17.1 low 29.7 30.6 29.6 auto-negotia- tion complete 1.5 auto-negoti- ate com- plete rising 1.5 1.5 low 29.6 30.5 29.5 remote fault detected 1.4 remote fault rising 1.4 1.4 low 29.5 30.4 29.4 link down 1.2 link status falling 1.2 1.2 high 29.4 30.3 29.3 auto-negotia- tion lp acknowl- edge 5.14 acknowl- edge rising 5.14 5.14 low 29.3 30.2 29.2 parallel detec- tion fault 6.4 parallel detection fault rising 6.4 6.4 low 29.2 30.1 29.1 auto-negotia- tion page received 6.1 page received rising 6.1 6.1 low 29.1 downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 131 lan9252 note 5: wol_int is defined as bits 7:4 in the phy x wakeup control and status register (phy_wucsr_x) anded with bits 3:0 of the same register, wi th the resultant 4 bits ored together. 11.2.8 phy power-down modes there are two phy power-down modes: general power-down mode and energy detect power-down mode. these modes are described in the following subsections. 11.2.8.1 general power-down this power-down mode is controlled by the power down (phy_pwr_dwn) bit of the phy x basic control register (phy_basic_control_x) . in this mode the entire tr ansceiver, except the phy management control interface, is powered down. the transceiver will remain in this power-down state as long as the power down (phy_pwr_dwn) bit is set. when the power down (phy_pwr_dwn) bit is cleared, the transceiver powers up and is automatically reset. 11.2.8.2 energy de tect power-down this power-down mode is enabled by setting the energy detect power-down (edpwrdown) bit of the phy x mode control/status register (phy_mode_control_status_x) . in this mode, when no energy is present on the line, the entire transceiver is powered down (exc ept for the phy management control inte rface, the squelch circuit and the energyon logic). the energyon logic is used to detect the presence of valid energy from 100base-tx, 10base- t, or auto-negotiation signals. in this mode, when the energy on (energyon) bit in the phy x mode control/status register (phy_mode_con- trol_status_x) signal is low, the transceiver is powered down and nothing is transmitted. when energy is received, via link pulses or packets, the energy on (energyon) bit goes high, and the transceiver powers up. the transceiver automatically resets itself into the st ate prior to power-down, and asserts the int7 bit of the phy x interrupt source flags register (phy _interrupt_source_x) . the first and possibly second packet to activate energyon may be lost. when the energy detect power-down (edpwrdown) bit of the phy x mode control/status register (phy_mode_- control_status_x) is low, energy detect power-down is disabled. when in edpd mode, the devices nlp characteristics may be modified. the device can be configured to transmit nlps in edpd via the edpd tx nlp enable bit of the phy x edpd nlp / crossover ti me / eee configur ation register (phy_edpd_cfg_x) . when enabled, the tx nlp time interval is configurable via the edpd tx nlp interval timer select field of the phy x edpd nlp / crossover time / eee co nfiguration r egister (phy_edpd_cfg_x) . when in edpd mode, the device can also be configured to wa ke on the reception of one or two nlps. setting the edpd rx single nlp wake enable bit of the phy x edpd nlp / crossover time / eee configuration register (phy_edpd_cf- g_x) will enable the device to wake on reception of a single nlp. if the edpd rx single nlp wake enable bit is cleared, the maximum interval for detecting reception of two nlps to wake from edpd is configurable via the edpd rx nlp max interval detect select field of the phy x edpd nlp / crossover time / eee configuration register (phy_edp- d_cfg_x) . the energy detect power down feature is part of the broad er power management features of the device and can be used to trigger the power management even t or general interrupt request pin ( irq ). this is accomplished by enabling the energy detect power-down feature of t he phy as described above, and setting the corresponding energy detect enable (bit 14 for phy a, bit 15 for phy b) of the power management control register (pmt_ctrl) . refer to power manage- ment for additional information. note: the energy on (energyon) bit in the phy x mode control/status register (phy_mode_con- trol_status_x) is defaulted to a 1 at the start of th e signal acquisition process, therefore the int7 bit in the phy x interrupt source flags register (phy_interrupt_source_x) will also read as a 1 at power-up. if no signal is present, then both energy on (energyon) and int7 will clear within a few mil- liseconds. note: for more information on the various power ma nagement features of the device, refer to section 6.3, "power management," on page 43 . the power-down modes of each phy are controlled independently. the phy power-down modes do not reload or reset the phy registers. downloaded from: http:///
lan9252 ds00001909a-page 132 ? 2015 microchip technology inc. 11.2.9 wake on lan (wol) the phy supports layer wol event detection of perf ect da, broadcast, magic packet, and wakeup frames. each type of supported wake event (perfect da, broadca st, magic packet, or wakeup frames) may be individually enabled via perfect da wakeup enable (pfda_en) , broadcast wakeup enable (bcst_en) , magic packet enable (mpen) , and wakeup frame enable (wuen) bits of the phy x wakeup control and status register (phy_wucsr_x) , respectively. the wol event is indicated via the int8 bit of the phy x interrupt source flags register (phy_inter- rupt_source_x) . the wol feature is part of the broader power management features of the device and can be used to trigger the power management event or general interrupt request pin ( irq ). this is accomplished by enabling the wol feature of the phy as described above, and setting the corresponding wol enable (bit 14 for phy a, bit 15 for phy b) of the power man- agement control register (pmt_ctrl) . refer to section 6.3, "power management," on page 43 for additional informa- tion. the phy x wakeup control and status register (phy_wucsr_x) also provides a wol configured bit, which may be set by software after all wol registers are configured. bec ause all wol related registers are not affected by software resets, software can poll the wol configured bit to ensure all wol registers are fu lly configured. this allows the software to skip reprogramming of the wol regist ers after reboot due to a wol event. the following subsections detail each type of wol event. for additional information on the main system interrupts, refer to section 8.0, "system interrupts," on page 53 . 11.2.9.1 perfect da (destination address) detection when enabled, the perfect da detection mode allows the detection of a frame with t he destination address matching the address stored in the phy x mac receive address a register (phy_rx_addra_x) , phy x mac receive address b register (phy_rx_addrb_x) , and phy x mac receive address c register (phy_rx_addrc_x) . the frame must also pass the fcs and packet length check. as an example, the host system must perform the following steps to enable the device to detect a perfect da wol event: 1. set the desired mac address to cause the wake event in the phy x mac receive address a register (phy_rx- _addra_x) , phy x mac receive address b register (phy_rx_addrb_x) , and phy x mac receive address c register (phy_rx_addrc_x) . 2. set the perfect da wakeup enable (pfda_en) bit of the phy x wakeup control and status register (phy_wucsr_x) to enable perfect da detection. 3. set bit 8 (wol event indicator) in the phy x interrupt mask regist er (phy_interrupt_mask_x) to enable wol events. when a match is triggered, bit 8 of the phy x interrupt source flags re gister (phy_int errupt_source_x) will be set, and the perfect da frame received (pfda_fr) bit of the phy x wakeup control and status register (phy_wucsr_x) will be set. 11.2.9.2 broadcast detection when enabled, the broadcast detection m ode allows the detection of a frame with the destination address value of ff ff ff ff ff ff. the frame must also pass the fcs and packet length check. as an example, the host system must perform the following st eps to enable the device to detect a broadcast wol event: 1. set the broadcast wakeup enable (bcst_en) bit of the phy x wakeup control and status register (phy_wucsr_x) to enable broadcast detection. 2. set bit 8 (wol event indicator) in the phy x interrupt mask regist er (phy_interrupt_mask_x) to enable wol events. when a match is triggered, bit 8 of the phy x interrupt source flags re gister (phy_int errupt_source_x) will be set, and the broadcast frame received (bcast_fr) bit of the phy x wakeup control and status register (phy_wucsr_x) will be set. 11.2.9.3 magic packet detection when enabled, the magic packet detection mode allows the detection of a magic packet frame. a magic packet is a frame addressed to the device - either a unicast to the progr ammed address, or a broadcast - which contains the pattern 48h ff_ff_ff_ff_ff_ff after the destination and source address field, followed by 16 repet itions of the desired mac address (loaded into the phy x mac receive address a register (phy_rx_addra_x) , phy x mac receive address downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 133 lan9252 b register (phy_rx_addrb_x) , and phy x mac receive address c register (phy_rx_addrc_x) ) without any breaks or interruptions. in case of a break in th e 16 address repetitions, the logic scans for the 48h ff_ff_ff_ff_ff_ff pattern again in the incoming frame. the 16 repetitions may be anywhere in the frame but must be preceded by the synchronization stream. the frame mu st also pass the fcs check and packet length checking. as an example, if the desired address is 00h 11h 22h 33h 44h 55h, then the logic scans for the following data sequence in an ethernet frame: destination address source ad dress ff ff ff ff ff ff 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 fcs as an example, the host system must perform the following steps to enable the device to detect a magic packet wol event: set the desired mac address to cause the wake event in the phy x mac receive address a register (phy_rx_ad- dra_x) , phy x mac receive address b register (phy_rx_addrb_x) , and phy x mac receive address c register (phy_rx_addrc_x) . set the magic packet enable (mpen) bit of the phy x wakeup control and status register (phy_wucsr_x) to enable magic packet detection. set bit 8 (wol event indicator) in the phy x interrupt mask regist er (phy_interrupt_mask_x) to enable wol events. when a match is triggered, bit 8 of the phy x interrupt source flags re gister (phy_int errupt_source_x) will be set, and the magic packet received (mpr) bit of the phy x wakeup control and status register (phy_wucsr_x) will be set. 11.2.9.4 wakeup frame detection when enabled, the wakeup frame detection mode allows t he detection of a pre-progra mmed wakeup frame. wakeup frame detection provides a wa y for system designers to de tect a customized pattern within a packet via a programma- ble wake-up frame filter. the filter has a 128-bit byte mask that indicates which bytes of the frame should be compared by the detection logic. a crc-16 is calculated over these byte s. the result is then compar ed with the filters respective crc-16 to determine if a match exists. w hen a wake-up pattern is received, the remote wakeup frame received (wufr) bit of the phy x wakeup control and status register (phy_wucsr_x) is set. if enabled, the filter can also incl ude a comparison between the frames dest ination address and the address specified in the phy x mac receive address a register (phy_rx_addra_x) , phy x mac receive address b register (phy_rx_addrb_x) , and phy x mac receive address c register (phy_rx_addrc_x). the specified address can be a unicast or a multicast. if address matching is enable d, only the programmed unicast or multicast address will be considered a match. non-specific multicast addresses and the broadcast address can be separately enabled. the address matching results are logically ord (i.e., specific address match result or any multicast result or broadcast result). whether or not the filter is enabled and whether the desti nation address is checked is determined by configuring the phy x wakeup filter configuration register a (phy_wuf_cfga_x). before enabling the filter , the application program must provide the detection logic with the sample frame and corresponding byte mask. this information is provided by writing the phy x wakeup filter configuration register a (phy_wuf_cfga_x), phy x wakeup filter configu ration register b (phy_wuf_cfgb_x) , and phy x wakeup filter byte mask registers (phy_wuf_mask_x) . the starting offset within the frame and the expected crc -16 for the filter is determined by the filter pattern offset and filter crc- 16 fields, respectively. if remote wakeup mode is enabled, the remote wakeup function checks each frame against the filter and recognizes the frame as a remote wakeup frame if it passes the filters address filtering and crc value match. the pattern offset defines the location of the first byte that should be checked in the frame. the byte mask is a 128-bit field that specifies whether or not each of the 128 contiguous bytes within the frame, beginning with the pattern offset, should be checked. if bit j in the byte mask is set, the detection logic checks the byte (patte rn offset + j) in the frame, otherwise byte (pattern offset + j) is ignored. downloaded from: http:///
lan9252 ds00001909a-page 134 ? 2015 microchip technology inc. at the completion of the crc-16 checking process, the c rc-16 calculated using the patt ern offset and byte mask is compared to the expected crc-16 value associated with the f ilter. if a match occurs, a remote wake-up event is sig- naled. the frame must also pass the fcs check and packet length checking. table 11-4 indicates the cases that produce a wake-up event. all other cases do not generate a wake-up event. as an example, the host system must per form the following steps to enable the device to de tect a wakeup frame wol event: declare pattern: 1. update the phy x wakeup filter byte ma sk registers (phy_wuf_mask_x) to indicate the valid bytes to match. 2. calculate the crc-16 value of va lid bytes offline and update the phy x wakeup filter configuration register b (phy_wuf_cfgb_x) . crc-16 is calculated as follows: at the start of a frame, crc-16 is initialized with th e value ffffh. crc-16 is updated when the pattern offset and mask indicate the received byte is part of the checksum calculation. the following algorithm is used to update the crc-16 at that time: let: ^ denote the exclusive or operator. data [7:0] be the received data byte to be included in the checksum. crc[15:0] contain the calc ulated crc-16 checksum. f0 f7 be intermediate results, calculated when a data byte is determined to be part of the crc-16. calculate: f0 = crc[15] ^ data[0] f1 = crc[14] ^ f0 ^ data[1] f2 = crc[13] ^ f1 ^ data[2] f3 = crc[12] ^ f2 ^ data[3] f4 = crc[11] ^ f3 ^ data[4] f5 = crc[10] ^ f4 ^ data[5] f6 = crc[09] ^ f5 ^ data[6] f7 = crc[08] ^ f6 ^ data[7] the crc-32 is updated as follows: crc[15] = crc[7] ^ f7 crc[14] = crc[6] crc[13] = crc[5] crc[12] = crc[4] crc[11] = crc[3] table 11-4: wakeup generation cases filter enabled frame type crc matches address match enabled any mcast enabled bcast enabled frame address matches yes unicast yes no x x x yes unicast yes yes x x yes yes multicast yes x yes x x yes multicast yes yes no x yes yes broadcast yes x x yes x downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 135 lan9252 crc[10] = crc[2] crc[9] = crc[1] ^ f0 crc[8] = crc[0] ^ f1 crc[7] = f0 ^ f2 crc[6] = f1 ^ f3 crc[5] = f2 ^ f4 crc[4] = f3 ^ f5 crc[3] = f4 ^ f6 crc[2] = f5 ^ f7 crc[1] = f6 crc[0] = f7 3. determine the offset pattern with offset 0 being the first byte of the destination addre ss. update the offset in the filter pattern offset field of the phy x wakeup f ilter configuration regist er a (phy_wuf_cfga_x). determine address ma tching conditions: 4. determine the address matching scheme based on ta b l e 11 - 4 and update the filter broadcast enable , filter any multicast enable , and address match enable bits of the phy x wakeup filter configuration register a (phy_wuf_cfga_x) accordingly. 5. if necessary (see step 4), set the desired mac address to cause the wake event in the phy x mac receive address a register (phy_rx_addra_x) , phy x mac receive address b register (phy_rx_addrb_x) , and phy x mac receive address c register (phy_rx_addrc_x) . 6. set the filter enable bit of the phy x wakeup filter configurati on register a (phy_wuf_cfga_x) to enable the filter. enable wakeup frame detection: 7. set the wakeup frame enable (wuen) bit of the phy x wakeup control and status register (phy_wucsr_x) to enable wakeup frame detection. 8. set bit 8 (wol event indicator) in the phy x interrupt mask regist er (phy_interrupt_mask_x) to enable wol events. when a match is triggered, the remote wakeup frame received (wufr) bit of the phy x wakeup control and status register (phy_wucsr_x) will be set. to provide additional visibility to software, the filter triggered bit of the phy x wakeup filter configuration register a (phy_wuf_cfga_x) will be set. 11.2.10 resets in addition to the chip-level hardware reset ( rst# ), ethercat system reset, and powe r-on reset (por), the phy sup- ports three block specific resets. these are discussed in th e following sections. for detailed information on all device resets and the reset sequence refer to section 6.2, "resets," on page 38 . 11.2.10.1 phy software reset via reset_ctl the phys can be reset via the reset control register (reset_ctl) . these bits are self clearing after approximately 102 us. this reset does not reload the config uration strap values into the phy registers. 11.2.10.2 phy software reset via phy_basic_ctrl_x the phy can also be reset by setting the soft reset (phy_srst) bit of the phy x basic control register (phy_ba- sic_control_x) . this bit is self clearing and will return to 0 after the reset is comp lete. this reset does not reload the configuration strap values into the phy registers. note: only a hardware reset ( rst# ), power-on reset (por) or ethercat system reset will automatically reload the configuration strap values into the phy registers. the digital reset (digital_rst) bit in the reset control regi ster (reset_ctl) does not reset the phys. for all other phy resets, phy registers will need to be manually configured via software. downloaded from: http:///
lan9252 ds00001909a-page 136 ? 2015 microchip technology inc. 11.2.10.3 phy power-down reset after the phy has returned from a power-down state, a re set of the phy is automatically generated. the phy power- down modes do not reload or rese t the phy registers. refer to section 11.2.8, "phy power-down modes," on page 131 for additional information. 11.2.11 link integrity test the device performs the lin k integrity test as outlined in the ieee 802.3u (c lause 24-15) link moni tor state diagram. the link status is multiplexed with the 10 mbps link status to form the link status bit in the phy x basic status register (phy_basic_status_x) and to drive the link led functions. the dsp indicates a valid mlt-3 waveform present on the rxpx and rxnx signals as defined by the ansi x3.263 tp- pmd standard, to the link monitor state-machine, us ing the internal data_valid signal. when data_valid is asserted, the control logic moves into a link-ready state and waits for an enable from the auto-negotiation block. when received, the link-up state is entered, and the transmit and receive logic blocks become active. should auto-negoti- ation be disabled, the link integrity logic moves immediat ely to the link-up state when the data_valid is asserted. to allow the line to stabilize, the link integrity logic will wait a minimum of 330 ms from the time data_valid is asserted until the link-ready state is entered. should the data_valid input be negat ed at any time, this logic will immediately negate the link signal and enter the link-down state. 11.2.12 cable diagnostics the phys provide cable diagnostics which allow for open/short and length detection of the ethernet cable. the cable diagnostics consist of two primary modes of operation: time domain reflectometry (tdr) cable diagnostics tdr cable diagnostics enable the detection of open or shor ted cabling on the tx or rx pair, as well as cable length estimation to the open/short fault. matched cable diagnostics matched cable diagnostics enable cable length estimation on 100 mbps-linked cables. refer to the following sub-sections for details on proper operation of each cable diagnostics mode. 11.2.12.1 time domain reflectometry (tdr) cable diagnostics the phys provide tdr cable diagnostics which enable the detecti on of open or shorted cabli ng on the tx or rx pair, as well as cable length estimation to the open/short faul t. to utilize the tdr cable diagnostics, auto-mdix and auto negotiation must be disabled, and the phy must be forced to 100 mbps full-duplex mode. these actions must be per- formed before setting the tdr enable bit in the phy x tdr control/status register (phy_tdr_control_stat_x) . with auto-mdix disabled, the tdr will test the tx or rx pair selected by register bit 27.13 ( auto-mdix state (amdix- state) ). proper cable testing should include a test of each pair. tdr cable diagnostics is not app ropriate for 100base- fx mode. when tdr testing is complete, prior register settings may be restored. figure 11-5 provides a flow diagram of proper tdr usage. note: cable diagnostics are not used for 100base-fx mode. downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 137 lan9252 the tdr operates by transmitting pulses on the selected twisted pair within the ethernet cable (tx in mdi mode, rx in mdix mode). if the pair being tested is open or shorted, the resulting impedance discontinuity results in a reflected signal that can be detected by the phy. the phy measures the time between the transmitted signal and received reflec- tion and indicates the results in the tdr channel length field of the phy x tdr control/status register (phy_tdr_- control_stat_x) . the tdr channel length field indicates the electrical length of the cable, and can be multiplied by the appropriate propagation constant in ta b l e 11 - 5 to determine the approximate physical distance to the fault. figure 11-5: tdr usage flow diagram note: the tdr function is typically used when the link is inoperable. however, an active link will drop when oper- ating the tdr. disable amdix and force mdi (or mdix) write phy reg 27: 0x8000 (mdi) - or - write phy reg 27: 0xa000 (mdix) tdr channel status complete? disable aneg and force 100mb full- duplex write phy reg 0: 0x2100 enable tdr write phy reg 25: 0x8000 no reg 25.8 == 0 yes reg 25.8 == 1 check tdr control/status register read phy reg 25 save: tdr channel type (reg 25.10:9) tdr channel length (reg 25.7:0) mdix case tested? yes repeat testing in mdix mode done start downloaded from: http:///
lan9252 ds00001909a-page 138 ? 2015 microchip technology inc. since the tdr relies on the reflected si gnal of an improperly terminated cable, th ere are several factors that can affect the accuracy of the physical length estimate. these include: 1. cable type (cat 5, cat5e, cat6): the electrical length of each cable type is slightly different due to the twists- per-meter of the internal signal pairs and differences in signal propagation spee ds. if the cable type is known, the length estimate can be calculated more accurately by using the propagation constant appropriate for the cable type (see table 11-5 ). in many real-world applications the cable type is unknown, or may be a mix of different cable types and lengths. in this case, use the propagation constant for the unknown cable type. 2. tx and rx pair: for each cable type, the eia standards specify different twist rates (twists-per-meter) for each signal pair within the ethernet cable. this results in different measurements for the rx and tx pair. 3. actual cable length: the difference between the estimated cable le ngth and actual cable length grows as the physical cable length increases, with the most accurate results at less than approximately 100 m. 4. open/short case: the open and shorted cases will return diff erent tdr channel length values (electrical lengths) for the same physical distance to the fault. comp ensation for this is achieved by using different propa- gation constants to calculate the physical length of the cable. for the open case, the estimated distance to the fault can be calculated as follows: distance to open fault in meters ?? tdr channel length * p open where: p open is the propagation c onstant selected from ta b l e 11 - 5 for the shorted case, the estimated distance to the fault can be calculated as follows: distance to open fault in meters ? tdr channel length * p short where: p short is the propagation constant selected from table 11-5 the typical cable length measurement margin of error for open and shorted cases is dependent on the selected cable type and the distance of the open/short from the device. ta b l e 11 - 6 and table 11-7 detail the typical measurement error for open and shorted cases, respectively. table 11-5: tdr propagation constants tdr propagation constant cable type unknown cat 6 cat 5e cat 5 p open 0.769 0.745 0.76 0.85 p short 0.793 0.759 0.788 0.873 table 11-6: typical measurement error for open cable (+/- meters) physical distance to fault selected propagation constant p open = unknown p open = cat 6 p open = cat 5e p open = cat 5 cat 6 cable, 0-100 m 96 cat 5e cable, 0-100 m 5 5 cat 5 cable, 0-100 m 13 3 cat 6 cable, 101-160 m 14 6 cat 5e cable, 101-160 m 8 6 cat 5 cable, 101-160 m 20 6 downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 139 lan9252 11.2.12.2 matched cable diagnostics matched cable diagnostics enable cable length estimation on 100 mbps-linked cables of up to 120 meters. if there is an active 100 mb link, the approximate distance to the link partner can be estimated using the phy x cable length register (phy_cable_len_x) . if the cable is properly terminat ed, but there is no active 100 mb link (the link partner is disabled, nonfunctional, the link is at 10 mb, etc.), the cable length cannot be estimated and the phy x cable length register (phy_cable_len_x) should be ignored. the estimated distance to the link partner can be determined via the cable length (cbln) field of the phy x cable length register (phy_cable_len_x) using the lookup table provided in table 11-8 . the typical cable length measurement margin of erro r for a matched cable case is +/- 20 m. the matched cable length margin of error is consistent for all cable types from 0 to 120 m. table 11-7: typical measurement erro r for shorted cable (+/- meters) physical distance to fault selected propagation constant p short = unknown p short = cat 6 p short = cat 5e p short = cat 5 cat 6 cable, 0-100 m 85 cat 5e cable, 0-100 m 5 5 cat 5 cable, 0-100 m 11 2 cat 6 cable, 101-160 m 14 6 cat 5e cable, 101-160 m 7 6 cat 5 cable, 101-160 m 11 3 table 11-8: match case estimated cable length (cbln) lookup cbln field value estimated cable length 0 - 3 0 4651 7 62 7 73 8 84 9 95 9 10 70 11 81 12 91 13 102 14 113 15 123 downloaded from: http:///
lan9252 ds00001909a-page 140 ? 2015 microchip technology inc. 11.2.13 loopback operation the phys may be configured for near-end loopback and connector loopback. these loopback modes are detailed in the following subsections. 11.2.13.1 near-end loopback near-end loopback mode sends the digital transmit data back out the receive data signals for testing purposes, as indi- cated by the blue arrows in figure 11-6 . the near-end loopback mode is enabled by setting the loopback (phy_loop- back) bit of the phy x basic control regist er (phy_basic_control_x) to 1. a large percentage of the digital circuitry is operational in near-end loopback mode because data is routed through the pcs and pma layers into the pmd sublayer before it is looped back. the col signal will be inactive in this mode, unless collision test mode (phy_col_test) is enabled in the phy x basic control register (phy_basic_control_x) . the transmitters are powered down regardless of the state of the internal mii txen signal. 11.2.13.2 connector loopback the device maintains reliable transmission over very short cables and can be tested in a connector loopback as shown in figure 11-7 . an rj45 loopback cable can be used to route the transmit signals from the output of the transformer back to the receiver inputs. the loopback works at both 10 and 100 mbps. note: for a properly terminated cable (match case), t here is no reflected signal. in this case, the tdr channel length field is invalid and should be ignored. figure 11-6: near-end loopback block diagram figure 11-7: connection loopback block diagram 10/100 ethernet mac cat-5 xfmr digital rxd txd analog rx tx xx 10/100 ethernet mac xfmr digital rxd txd analog rx tx 12 3 4 5 6 7 8 rj45 loopback cable. created by connecting pin 1 to pin 3 and connecting pin 2 to pin 6. downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 141 lan9252 11.2.14 100base-fx operation when set for 100base-fx operati on, the scrambler and mtl-3 blocks are disable and the analog rx and tx pins are changed to differential lvpecl pins and connect through extern al terminations to the external fiber transceiver. the differential lvpecl pins support a signal voltage range compatible with sff (lvpecl) and sfp (reduced lvpecl) type transceivers. while in 100base-fx operation, the quality of the receive sign al is provided by the exter nal transceiver as either an open-drain, cmos level, loss of signal (sfp) or a lvpecl signal detect (sff). 11.2.14.1 100base-fx far end fault indication since auto-negotiation is not specifi ed for 100base-fx, its remote fault capabi lity is unavailabl e. instead, 100base- fx provides an optional far-end fault function. when no signal is being received, the far-end fault feature transmits a specia l far-end fault indication to its far-end peer. the far-end fault indication is sent only when a physical error condition is sensed on the receive channel. the far-end fault i ndication is comprised of three or more repeating cycles, ea ch of 84 ones followed by a single zero. this signal is sent in-band and is readily detectable but is constructed so as to not satisfy the 100base-x carrier sense criterion. far-end fault is implemented through the far-end fault g enerate, far-end fault detect, and the link monitor pro- cesses. the far-end fault generate process is responsible for sensing a receive channel failure (signal_status=off) and transmitting the far-end fault indication in response. the transmission of the far-end fault indication may start or stop at any time depending only on signal_status. the far- end fault detect process continuously monitors the rx pro- cess for the far-end fault indication. dete ction of the far-end fault indication di sables the station by causing the link monitor process to de-assert link_status, which in turn causes the station to source idles. far-end fault is enabled by default while in 100base-fx mode via the far end fault indicati on enable (fefi_en) of the phy x special control/status indication register (phy _special_control_stat_ind_x) . 11.2.14.2 100base-fx enable and los/sd selection 100base-fx operation is enabled by the use of the fx mode straps ( fx_mode_strap_1 and fx_mode_strap_2 ) and is reflected in the 100base-fx mode (fx_mode) bit in the phy x special modes regist er (phy_special_modes_x) . loss of signal mode is selected for both phys by the three level fxlosen strap input pin. the three levels correspond to loss of signal mode for a) neither phy (less than 1 v (typ.)), b) phy a (greater than 1 v (t yp.) but less than 2 v (typ.)) or c) both phys (greater than 2 v (t yp.)). it is not possible to select loss of signal mode for only phy b. if loss of signal mode is not selected, then signal detect mode is selected, independently, by the fxsdena or fxs- denb strap input pin. when greater than 1 v (typ.), signal detect mode is enabled, when less than 1 v (typ.), copper twisted pair is enabled. table 11-9 and table 11-10 summarize the selections. note: the fxsdena strap input pin is shared with the fxsda pin and the fxsdenb strap input pin is shared with the fxsdb pin. as such, the lvpecl levels ensure that the input is gr eater than 1 v (typ.) and that signal detect mode is selected. when tp copper is desired, the signal detect input function is not required and the pin should be set to 0 v. care must be taken such that an non-powered or disa bled transceiver does not load the signal detect input below the valid lvpecl level. table 11-9: 100base-fx los, sd and tp copper selection phy a fxlosen fxsdena phy mode <1 v (typ.) <1 v (typ.) tp copper >1 v (typ.) 100base-fx signal detect >1 v (typ.) n/a 100base-fx los downloaded from: http:///
lan9252 ds00001909a-page 142 ? 2015 microchip technology inc. 11.2.15 required ethernet magnetics (100base-tx) the magnetics selected for use with the device should be an auto-mdix style magnetic, which is widely available from several vendors. please review the smsc/microchip appl ication note 8.13 suggested magnetics for the latest quali- fied and suggested magnetics. a list of vendors and pa rt numbers are provided wi thin the application note. 11.2.16 phy registers phys a and b are comparable in functionality and have an identical set of non-memory mapped registers. these reg- isters are indirectly accessed through the mii management control/status register , phy address register , phy reg- ister address register , phy data register , mii management ecat access state register , and mii management ecat access state register . because phy a and b registers are functionally identical, their register descriptions have been consolidated. a lower- case x has been appended to the end of each phy register na me in this section, where x hold be replaced with a or b for the phy a or phy b registers respectively. in some instances, a 1 or a 2 may be appropriate instead. a list of the mii serial accessible control and status regist ers and their corresponding register index numbers is included in ta b l e 11 - 11 . each individual phy is assigned a unique phy address as detailed in section 11.1.1, "phy addressing," on page 120 . in addition to the mii serial accessible control and status re gisters, a set of indirectly ac cessible registers provides sup- port for the ieee 802.3 section 45.2 mdio manageable device (mmd) registers . a list of these registers and their cor- responding register index numbers is included in table 11-14 . control and status registers table 11-11 provides a list of supported registers. register details , including bit definitions, are provided in the following subsections. unless otherwise specified, reserved fields must be written with zeros if the register is written. table 11-10: 100base-fx los, sd and tp copper selection phy b fxlosen fxsdenb phy mode <1 v (typ.) <1 v (typ.) tp copper >1 v (typ.) 100base-fx signal detect >2 v (typ.) n/a 100base-fx los table 11-11: phy a and b mii serially accessible control and status registers index register name (symbol) group 0 phy x basic control regist er (phy_basic_control_x) basic 1 phy x basic status register (phy_basic_status_x) basic 2 phy x identification msb register (phy_id_msb_x) extended 3 phy x identification lsb register (phy_id_lsb_x) extended 4 phy x auto-negotiation advertisement register (phy_an_adv_x) extended 5 phy x auto-negotiation link partner base page ability register (phy_an_lp_base_ability_x) extended 6 phy x auto-negotiation expa nsion register (phy_an_exp_x) extended 7 phy x auto negotiation next page tx register (phy_an_np_tx_x) extended 8 phy x auto negotiation next page rx register (phy_an_np_rx_x) extended downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 143 lan9252 13 phy x mmd access control register (phy_mmd_access) extended 14 phy x mmd access address/data register (phy_mmd_addr_data) extended 16 phy x edpd nlp / crossover time / eee co nfiguration register (phy_edpd_cfg_x) vendor- specific 17 phy x mode control/status regist er (phy_mode_control_status_x) vendor- specific 18 phy x special modes register (phy_special_modes_x) vendor- specific 24 phy x tdr patterns/delay control register (phy_tdr_pat_delay_x) vendor- specific 25 phy x tdr control/status regi ster (phy_tdr_control_stat_x) vendor- specific 26 phy x symbol error counter register vendor- specific 27 phy x special control/status indi cation register (phy_special_con- trol_stat_ind_x) vendor- specific 28 phy x cable length register (phy_cable_len_x) vendor- specific 29 phy x interrupt source flags r egister (phy_interrupt_source_x) vendor- specific 30 phy x interrupt mask register (phy_interrupt_mask_x) vendor- specific 31 phy x special control/status regist er (phy_special_control_status_x) vendor- specific table 11-11: phy a and b mii serially accessible control and status registers index register name (symbol) group downloaded from: http:///
lan9252 ds00001909a-page 144 ? 2015 microchip technology inc. 11.2.16.1 phy x basic control register (phy_basic_control_x) this read/write register is used to configure the phy. index (decimal): 0 size: 16 bits bits description type default 15 soft reset (phy_srst) when set, this bit resets all the phy r egisters to their default state, except those marked as nasr type. this bit is self clearing. 0: normal operation 1: reset r/w sc 0b 14 loopback (phy_loopback) this bit enables/disables the loopback mode. when enabled, transmissions are not sent to network. instead, they are looped back into the phy. 0: loopback mode disabled (normal operation) 1: loopback mode enabled r/w 0b 13 speed select lsb (phy_speed_sel_lsb) this bit is used to set the speed of the phy when the auto-negotiation enable (phy_an) bit is disabled. 0: 10 mbps 1: 100 mbps r/w 1b 12 auto-negotiation enable (phy_an) this bit enables/disables auto-n egotiation. when enabled, the speed select lsb (phy_speed_sel_lsb) and duplex mode (phy_duplex) bits are overridden. this bit is forced to a 0 if the 100base-fx mode (fx_mode) bit of the phy x special modes register (phy_special_modes_x) is a high. 0: auto-negotiation disabled 1: auto-negotiation enabled r/w note 6 11 power down (phy_pwr_dwn) this bit controls the power down mode of the phy. 0: normal operation 1: general power down mode r/w 0b 10 reserved ro - 9 restart auto-negotia tion (phy_rst_an) when set, this bit restarts the auto-negotiation process. 0: normal operation 1: auto-negotiation restarted r/w sc 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 145 lan9252 note 6: this field defaults to a 0 if in 100base-fx mode or to a 1 otherwise. ethercat always uses auto-negotiate, 100 mbps, full-duplex. 8 duplex mode (phy_duplex) this bit is used to set the duplex when the auto-negotiation enable (phy_an) bit is disabled. 0: half duplex 1: full duplex r/w 1b 7 collision test mode (phy_col_test) this bit enables/disables the collision test mode of the phy. when set, the collision signal is active during transmission. it is recommended that this fea- ture be used only in loopback mode. 0: collision test mode disabled 1: collision test mode enabled r/w 0b 6:0 reserved ro - bits description type default downloaded from: http:///
lan9252 ds00001909a-page 146 ? 2015 microchip technology inc. 11.2.16.2 phy x basic status register (phy_basic_status_x) this register is used to monitor the status of the phy. index (decimal): 1 size: 16 bits bits description type default 15 100base-t4 this bit displays the status of 100base-t4 compatibility. 0: phy not able to perform 100base-t4 1: phy able to perform 100base-t4 ro 0b 14 100base-x full duplex this bit displays the status of 100base-x full duplex compatibility. 0: phy not able to perf orm 100base-x full duplex 1: phy able to perfor m 100base-x full duplex ro 1b 13 100base-x half duplex this bit displays the status of 100base-x half duplex compatibility. 0: phy not able to perform 100base-x half duplex 1: phy able to perform 100base-x half duplex ro 1b 12 10base-t full duplex this bit displays the status of 10base-t full duplex compatibility. 0: phy not able to perform 10base-t full duplex 1: phy able to perfor m 10base-t full duplex ro 1b 11 10base-t half duplex (typ.) this bit displays the status of 10base-t half duplex compatibility. 0: phy not able to perform 10base-t half duplex 1: phy able to perform 10base-t half duplex ro 1b 10 100base-t2 full duplex this bit displays the status of 100base-t2 full duplex compatibility. 0: phy not able to perform 100base-t2 full duplex 1: phy able to perform 100base-t2 full duplex ro 0b 9 100base-t2 half duplex this bit displays the status of 100base-t2 half duplex compatibility. 0: phy not able to perform 100base-t2 half duplex 1: phy able to perform 100base-t2 half duplex ro 0b 8 extended status this bit displays whether extended status information is in register 15 (per ieee 802.3 clause 22.2.4). 0: no extended status information in register 15 1: extended status information in register 15 ro 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 147 lan9252 7 unidirectional ability this bit indicates whether the phy is able to transmit regardless of whether the phy has determined that a valid link has been established. 0: can only transmit when a valid link has been established 1: can transmit regardless ro 0b 6 mf preamble suppression this bit indicates whether the phy accepts management frames with the pre- amble suppressed. 0: management frames with preamble suppressed not accepted 1: management frames with preamble suppressed accepted ro 0b 5 auto-negotiation complete this bit indicates the status of the auto-negotiation process. 0: auto-negotiation process not completed 1: auto-negotiation process completed ro 0b 4 remote fault this bit indicates if a remote fault condition has been detected. 0: no remote fault condition detected 1: remote fault condition detected ro/lh 0b 3 auto-negotiation ability this bit indicates the phys auto-negotiation ability. 0: phy is unable to perform auto-negotiation 1: phy is able to pe rform auto-negotiation ro 1b 2 link status this bit indicates the status of the link. 0: link is down 1: link is up ro/ll 0b 1 jabber detect this bit indicates the status of the jabber condition. 0: no jabber condition detected 1: jabber condition detected ro/lh 0b 0 extended capability this bit indicates whether extended register capability is supported. 0: basic register set capabilities only 1: extended register set capabilities ro 1b bits description type default downloaded from: http:///
lan9252 ds00001909a-page 148 ? 2015 microchip technology inc. 11.2.16.3 phy x identification msb register (phy_id_msb_x) this read/write register contains the m sb of the organizationally unique identifier (oui) for the phy. the lsb of the phy oui is cont ained in the phy x identification lsb register (phy_id_lsb_x) . index (decimal): 2 size: 16 bits bits description type default 15:0 phy id this field is assigned to the 3rd through 18th bits of the oui, respectively (oui = 00800fh). r/w 0007h downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 149 lan9252 11.2.16.4 phy x identification lsb register (phy_id_lsb_x) this read/write register contains the lsb of the organizationally unique identifi er (oui) for the phy. the msb of the phy oui is cont ained in the phy x identification msb register (phy_id_msb_x) . index (decimal): 3 size: 16 bits bits description type default 15:10 phy id this field is assigned to the 19th through 24th bits of the phy oui, respec- tively. (oui = 00800fh). r/w c140h 9:4 model number this field contains the 6-bit manufacturers model number of the phy. r/w 3:0 revision number this field contain the 4-bit manufacturers revision number of the phy. r/w note: the default value of the revision number field may vary dependent on the silicon revision number. downloaded from: http:///
lan9252 ds00001909a-page 150 ? 2015 microchip technology inc. 11.2.16.5 phy x auto-negotiation advertisement register (phy_an_adv_x) this read/write register contains the advertised ability of the phy and is used in the auto-negotiation process with the link partner. index (decimal): 4 size: 16 bits bits description type default 15 next page 0 = no next page ability 1 = next page capable r/w 0b 14 reserved ro - 13 remote fault this bit determines if remote fault indication will be advertised to the link part- ner. 0: remote fault indication not advertised 1: remote fault indication advertised r/w 0b 12 extended next pagenote: this bit should be written as 0. r/w 0b 11 asymmetric pause this bit determines the advertised asymmetric pause capability. 0: no asymmetric pause toward link partner advertised 1: asymmetric pause toward link partner advertised r/w 0b 10 symmetric pause this bit determines the advertised symmetric pause capability. 0: no symmetric pause toward link partner advertised 1: symmetric pause toward link partner advertised r/w 0b 9 reserved ro - 8 100base-x full duplex this bit determines the advertised 100base-x full d uplex capability. 0: 100base-x full duplex ability not advertised 1: 100base-x full duplex ability advertised r/w 1b 7 100base-x half duplex this bit determines the advertised 100base-x half duplex capability. 0: 100base-x half duplex ability not advertised 1: 100base-x half duplex ability advertised r/w 0b 6 10base-t full duplex this bit determines the advertised 10base-t full duplex capability. 0: 10base-t full duplex ability not advertised 1: 10base-t full duplex ability advertised r/w 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 151 lan9252 5 10base-t half duplex this bit determines the advertise d 10base-t half duple x capability. 0: 10base-t half duplex ability not advertised 1: 10base-t half duplex ability advertised r/w 0b 4:0 selector field this field identifies the type of message being sent by auto-negotiation. 00001: ieee 802.3 r/w 00001b bits description type default downloaded from: http:///
lan9252 ds00001909a-page 152 ? 2015 microchip technology inc. 11.2.16.6 phy x auto-negotiation link partner base page ability register (phy_an_lp_base_ability_x) this read-only register contai ns the advertised ability of the link partners phy and is used in the auto-negotiation pro- cess between the link partner and the phy. index (decimal): 5 size: 16 bits bits description type default 15 next page this bit indicates the link partner phy page capability. 0: link partner phy does not ad vertise next page capability 1: link partner phy advertises next page capability ro 0b 14 acknowledge this bit indicates whether the link code word has been received from the partner. 0: link code word not yet received from partner 1: link code word received from partner ro 0b 13 remote fault this bit indicates whether a remote fault has been detected. 0: no remote fault 1: remote fault detected ro 0b 12 extended next page 0: link partner phy does not advertise extended next page capability 1: link partner phy advertises extended next page capability ro 0b 11 asymmetric pause this bit indicates the link partner phy asymmetric pause capability. 0: no asymmetric pause toward link partner 1: asymmetric pause toward link partner ro 0b 10 pause this bit indicates the link partner phy symmetric pause capability. 0: no symmetric pause toward link partner 1: symmetric pause toward link partner ro 0b 9 100base-t4 this bit indicates t he link partner phy 100base-t4 capability. 0: 100base-t4 ability not supported 1: 100base-t4 ability supported ro 0b 8 100base-x full duplex this bit indicates the link partner phy 100base- x full duplex capability. 0: 100base-x full duplex ability not supported 1: 100base-x full duplex ability supported ro 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 153 lan9252 7 100base-x half duplex this bit indicates the link partner phy 100base- x half duplex capability. 0: 100base-x half duplex ability not supported 1: 100base-x half duplex ability supported ro 0b 6 10base-t full duplex this bit indicates the link partner phy 10base-t full duplex capability. 0: 10base-t full duplex ability not supported 1: 10base-t full duplex ability supported ro 0b 5 10base-t half duplex this bit indicates the link partner phy 10base-t half duplex capability. 0: 10base-t half duplex ability not supported 1: 10base-t half duplex ability supported ro 0b 4:0 selector field this field identifies the type of message being sent by auto-negotiation. 00001: ieee 802.3 ro 00001b bits description type default downloaded from: http:///
lan9252 ds00001909a-page 154 ? 2015 microchip technology inc. 11.2.16.7 phy x auto-n egotiation expansion register (phy_an_exp_x) this read/write register is used in the auto-negotiation process between the link partner and the phy. index (decimal): 6 size: 16 bits bits description type default 15:7 reserved ro - 6 receive next page location able 0 = received next page storage location is not specified by bit 6.5 1 = received next page storage lo cation is specified by bit 6.5 ro 1b 5 received next page storage location 0 = link partner next pages are stored in the phy x auto-negotiation link partner base page ability regi ster (phy_an_lp_base_ability_x) (phy register 5) 1 = link partner next pages are stored in the phy x auto negotiation next page rx register (phy_an_np_rx_x) (phy register 8) ro 1b 4 parallel detection fault this bit indicates whether a parallel detection fault has been detected. 0: a fault hasnt been detected via the parallel detection function 1: a fault has been detected vi a the parallel de tection function ro/lh 0b 3 link partner next page able this bit indicates whether the link partner has next page ability. 0: link partner does not contain next page capability 1: link partner contains next page capability ro 0b 2 next page able this bit indicates whether the local device has next page ability. 0: local device does not contain next page capability 1: local device contains next page capability ro 1b 1 page received this bit indicates the reception of a new page. 0: a new page has not been received 1: a new page has been received ro/lh 0b 0 link partner auto -negotiation able this bit indicates the auto-negotiation ability of the link partner. 0: link partner is not auto-negotiation able 1: link partner is auto-negotiation able ro 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 155 lan9252 11.2.16.8 phy x auto negotiation next page tx register (phy_an_np_tx_x) index (in decimal): 7 size: 16 bits bits description type default 15 next page 0 = no next page ability 1 = next page capable r/w 0b 14 reserved ro - 13 message page 0 = unformatted page 1 = message page r/w 1b 12 acknowledge 2 0 = device cannot co mply with message. 1 = device will comply with message. r/w 0b 11 toggle 0 = previous value was high. 1 = previous value was low. ro 0b 10:0 message code message/unformatted code field r/w 000 0000 0001b downloaded from: http:///
lan9252 ds00001909a-page 156 ? 2015 microchip technology inc. 11.2.16.9 phy x auto negotiation next page rx register (phy_an_np_rx_x) index (in decimal): 8 size: 16 bits bits description type default 15 next page 0 = no next page ability 1 = next page capable ro 0b 14 acknowledge 0 = link code word not yet received from partner 1 = link code word received from partner ro 0b 13 message page 0 = unformatted page 1 = message page ro 0b 12 acknowledge 2 0 = device cannot comply with message. 1 = device will comply with message. ro 0b 11 toggle 0 = previous value was high. 1 = previous value was low. ro 0b 10:0 message code message/unformatted code field ro 000 0000 0000b downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 157 lan9252 11.2.16.10 phy x mmd access cont rol register (phy_mmd_access) this register in conjunction with the phy x mmd access address/data register (phy_mmd_addr_data) provides indirect access to the mdio manageable device (mmd) registers. refer to the mdio manageable device (mmd) reg- isters on page 175 for additional details. index (in decimal): 13 size: 16 bits bits description type default 15:14 mmd function this field is used to select the desired mmd function: 00 = address 01 = data, no post increment 10 = reserved 11 = reserved r/w 00b 13:5 reserved ro - 4:0 mmd device address (devad) this field is used to select the desired mmd device address. (3 = pcs, 7 = auto-negotiation) r/w 0h downloaded from: http:///
lan9252 ds00001909a-page 158 ? 2015 microchip technology inc. 11.2.16.11 phy x mmd access address/da ta register (phy_mmd_addr_data) this register in conjunction with the phy x mmd access control register (phy_mmd_access) provides indirect access to the mdio manageable device (mmd) registers. refer to the mdio manageable device (mmd) registers on page 175 for additional details. index (in decimal): 14 size: 16 bits bits description type default 15:0 mmd register address/data if the mmd function field of the phy x mmd access control register (phy_mmd_access) is 00, this field is used to indicate the mmd register address to read/write of the device specified in the mmd device address (devad) field. otherwise, this register is used to read/write data from/to the previously specified mmd address. r/w 0000h downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 159 lan9252 11.2.16.12 phy x edpd nlp / cr ossover time / eee configuration register (phy_edpd_cfg_x) this register is used to enable eee functionality and control nl p pulse generation and the auto-mdix crossover time of the phy. index (decimal): 16 size: 16 bits bits description type default 15 edpd tx nlp enable enables the generation of a normal link pulse (nlp) with a selectable inter- val while in energy detect power-down. 0=disabled, 1=enabled. the energy detect power-down (edpwrdown) bit in the phy x mode control/status register (phy_mode_control_status_x) needs to be set in order to enter energy detect power-down mode and the phy needs to be in the energy detect power-down state in order for this bit to generate the nlp. the edpd tx nlp independent mode bit of this register also needs to be set when setting this bit. r/w nasr note 7 0b 14:13 edpd tx nlp inte rval timer select specifies how often a nlp is transmitted while in the energy detect power- down state. 00b: 1 s 01b: 768 ms 10b: 512 ms 11b: 256 ms r/w nasr note 7 00b 12 edpd rx single nlp wake enable when set, the phy will wake upon the reception of a single normal link pulse. when clear, the phy requires two link pluses, within the interval spec- ified below, in order to wake up. single nlp wake mode is recommended when connecting to green net- work devices. r/w nasr note 7 0b 11:10 edpd rx nlp max interval detect select these bits specify the maximum time between two consecutive normal link pulses in order for them to be considered a valid wake up signal. 00b: 64 ms 01b: 256 ms 10b: 512 ms 11b: 1 s r/w nasr note 7 00b 9:4 reserved ro - 3 edpd tx nlp independent mode when set, each phy port independently detects power down for purposes of the edpd tx nlp function (via the edpd tx nlp enable bit of this register). when cleared, both ports need to be in a power-down state in order to gener- ate tx nlps during energy detect power-down. normally set this bit when setting edpd tx nlp enable . r/w nasr note 7 0b downloaded from: http:///
lan9252 ds00001909a-page 160 ? 2015 microchip technology inc. note 7: register bits designated as nasr are reset when the phy reset is generated via the reset control reg- ister (reset_ctl) . the nasr designation is only applicable when the soft reset (phy_srst) bit of the phy x basic control regist er (phy_basic_control_x) is set. 2 reserved ro - 1 edpd extend crossover when in energy detect power-down (edpd) mode ( energy detect power- down (edpwrdown) = 1), setting this bit to 1 extends the crossover time by 2976 ms. 0 = crossover time extension disabled 1 = crossover time extension enabled (2976 ms) r/w nasr note 7 0b 0 extend manual 10/100 auto-mdix crossover time when auto-negotiation is disabled, setting this bit extends the auto-mdix crossover time by 32 sample times (32 * 62 ms = 1984 ms). this allows the link to be established with a partner phy that has auto-negotiation enabled. when auto-negotiation is enabled, this bit has no affect. it is recommended that this bit is set when disabling an with auto-mdix enabled. r/w nasr note 7 1b bits description type default downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 161 lan9252 11.2.16.13 phy x mode control/status register (phy_mode_ control_status_x) this read/write register is us ed to control and monitor various phy configuration options. note 8: register bits designated as nasr are reset when the phy reset is generated via the reset control reg- ister (reset_ctl) . the nasr designation is only applicable when the soft reset (phy_srst) bit of the phy x basic control regist er (phy_basic_control_x) is set. index (decimal): 17 size: 16 bits bits description type default 15:14 reserved ro - 13 energy detect power-down (edpwrdown) this bit controls the energy detect power-down mode. 0: energy detect power-down is disabled 1: energy detect power-down is enabled note: when in edpd mode, the devices nlp characteristics can be modified via the phy x edpd nlp / crossover time / eee configuration register (phy_edpd_cfg_x) . r/w 0b 12:7 reserved ro - 6 altint alternate interrupt mode: 0 = primary interrupt system enabled (default) 1 = alternate interrupt system enabled refer to section 11.2.7, "phy interrupts," on page 128 for additional informa- tion. r/w nasr note 8 0b 5:2 reserved ro - 1 energy on (energyon) indicates whether energy is detected. this bit transitions to 0 if no valid energy is detected within 256 ms (1500 ms if auto-negotiation is enabled). it is reset to 1 by a hardware reset and by a software reset if auto-negotiation was enabled or will be enabled via strapping. refer to section 11.2.8.2, "energy detect power-down," on page 131 for additional information. ro 1b 0 reserved ro - downloaded from: http:///
lan9252 ds00001909a-page 162 ? 2015 microchip technology inc. 11.2.16.14 phy x special modes register (phy_special_modes_x) this read/write register is used to control the special modes of the phy. note 9: register bits designated as nasr are reset when the phy reset is generated via the reset control reg- ister (reset_ctl) . the nasr designation is only applicable when the soft reset (phy_srst) bit of the phy x basic control regist er (phy_basic_control_x) is set. note 10: the default value of this bit is determined by the fiber enable strap ( fx_mode_strap_1 for phy a, fx_- mode_strap_2 for phy b). note 11: this field defaults to 100b when in 100base-tx m ode (since ethercat only uses auto-negotiate, 100 mbps, full-duplex) or to 011b when in 100base-fx mode (since et hercat only uses 100 mbps, full- duplex). note 12: the default value of this field is determined per section 11.1.1, "phy addressing," on page 120 . index (decimal): 18 size: 16 bits bits description type default 15:11 reserved ro - 10 100base-fx mode (fx_mode) this bit enables 100base-fx mode note: fx_mode cannot properly be changed with this bit. this bit must always be written with its current va lue. device strapping must be used to set the desired mode. r/w nasr note 9 note 10 9:8 reserved ro - 7:5 phy mode (mode[2:0]) this field controls the phy mode of operation. refer to table 11-12 for a defi- nition of each mode. note: this field should be written with its read value. r/w nasr note 9 note 11 4:0 phy address (phyadd) the phy address field determines the mmi address to which the phy will respond and is also used for initialization of the cipher (scrambler) key. each phy must have a unique address. refer to section 11.1.1, "phy address- ing," on page 120 for additional information. note: no check is performed to ensure that this address is unique from the other phy addresses (phy a, phy b). r/w nasr note 9 note 12 table 11-12: mode[2:0] definitions mode[2:0] mode definitions 000 10base-t half duplex. au to-negotiation disabled. 001 10base-t full duplex. au to-negotiation disabled. 010 100base-tx or 100base-fx half duplex. au to-negotiation disabled. crs is active during transmit & receive. 011 100base-tx or 100base-fx full duplex. auto-negotiation disabled. crs is active during receive. downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 163 lan9252 100 100base-tx full duplex is advertised. auto-negotiation enabled. crs is active during receive. 101 reserved 110 power down mode. 111 all capable. auto-negotiation enabled. table 11-12: mode[2:0] definitions (continued) mode[2:0] mode definitions downloaded from: http:///
lan9252 ds00001909a-page 164 ? 2015 microchip technology inc. 11.2.16.15 phy x tdr patterns/delay co ntrol register (phy_tdr_pat_delay_x) note 13: register bits designated as nasr are reset when the phy reset is generated via the reset control reg- ister (reset_ctl) . the nasr designation is only applicable when the soft reset (phy_srst) bit of the phy x basic control regist er (phy_basic_control_x) is set. index (in decimal): 24 size: 16 bits bits description type default 15 tdr delay in 0 = line break time is 2 ms. 1 = the device uses tdr line break counter to increase the line break time before starting tdr. r/w nasr note 13 1b 14:12 tdr line break counter when tdr delay in is 1, this field specifies the increase in line break time in increments of 256 ms, up to 2 seconds. r/w nasr note 13 001b 11:6 tdr pattern high this field specifies the data patter n sent in tdr mode for the high cycle. r/w nasr note 13 101110b 5:0 tdr pattern low this field specifies the data pattern sent in tdr mode for the low cycle. r/w nasr note 13 011101b downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 165 lan9252 11.2.16.16 phy x tdr control/status register (phy_tdr_control_stat_x) note 14: register bits designated as nasr are reset when the phy reset is generated via the reset control reg- ister (reset_ctl) . the nasr designation is only applicable when the soft reset (phy_srst) bit of the phy x basic control regist er (phy_basic_control_x) is set. index (in decimal): 25 size: 16 bits bits description type default 15 tdr enable 0 = tdr mode disabled 1 = tdr mode enabled note: this bit self clears when tdr completes ( tdr channel status goes high) r/w nasr sc note 14 0b 14 tdr analog to digital filter enable 0 = tdr analog to digital filter disabled 1 = tdr analog to digital filter enabled (reduces noise spikes during tdr pulses) r/w nasr note 14 0b 13:11 reserved ro - 10:9 tdr channel cable type indicates the cable type det ermined by the tdr test. 00 = default 01 = shorted cable condition 10 = open cable condition 11 = match cable condition r/w nasr note 14 00b 8 tdr channel status when high, this bit indicates that the tdr operation has completed. this bit will stay high until reset or the tdr operation is restarted ( tdr enable = 1) r/w nasr note 14 0b 7:0 tdr channel length this eight bit value indicates the tdr channel length during a short or open cable condition. refer to section 11.2.12.1, "time domain reflectometry (tdr) cable diagnostics," on page 136 for additional information on the usage of this field. note: this field is not valid during a match cable condition. the phy x cable length register (phy_cable_len_x) must be used to determine cable length during a non-open/short (match) condition. refer to section 11.2.12, "cable diagnostics," on page 136 for additional information. r/w nasr note 14 00h downloaded from: http:///
lan9252 ds00001909a-page 166 ? 2015 microchip technology inc. 11.2.16.17 phy x symbol error counter register index (in decimal): 26 size: 16 bits bits description type default 15:0 symbol error coun ter (sym_err_cnt) this 100base-tx receiver-based error counter increments when an invalid code symbol is received, including idle symbols. the counter is incre- mented only once per packet, even when the received packet contains more than one symbol error. this field counts up to 65,536 and rolls over to 0 if incremented beyond its maximum value. note: this register is cleared on reset, but is not cleared by reading the register. it does not increment in 10base-t mode. ro 0000h downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 167 lan9252 11.2.16.18 phy x special control/ status indication register (p hy_special_control_stat_ind_x) this read/write register is used to control various options of the phy. note 15: register bits designated as nasr are reset when the phy reset is generated via the reset control reg- ister (reset_ctl) . the nasr designation is only applicable when the soft reset (phy_srst) bit of the phy x basic control regist er (phy_basic_control_x) is set. note 16: the default value of this bit is a 1 if in 100base-fx mode, otherwise the default is a 0. index (decimal): 27 size: 16 bits bits description type default 15 auto-mdix contro l (amdixctrl) this bit is responsible for determinin g the source of auto-mdix control for port x. 0: port x auto-mdix enabled 1: port x auto-mdix determined by bits 14 and 13 r/w nasr note 15 0b 14 auto-mdix enable (amdixen) when the amdixctrl bit of this register is set, this bit is used in conjunction with the amdixstate bit to control t he port auto-mdix functionality as shown in table 11-13 . auto-mdix is not appropriate and should not be enabled for 100base-fx mode. r/w nasr note 15 0b 13 auto-mdix state (amdixstate) when the amdixctrl bit of this register is set, this bit is used in conjunction with the amdixen bit to cont rol the port auto-mdix functionality as shown in table 11-13 . r/w nasr note 15 0b 12 reserved ro - 11 sqe test disable (sqeoff) this bit controls the disabling of th e sqe test (heartbeat). sqe test is enabled by default. 0: sqe test enabled 1: sqe test disabled r/w nasr note 15 0b 10:6 reserved ro - 5 far end fault indication enable (fefi_en) this bit enables far end fault generation and detection. see section 11.2.14.1, "100base-fx far end fa ult indication," on page 141 for more information. r/w note 16 4 10base-t polarity state (xpol) this bit shows the polarity state of the 10base-t. 0: normal polarity 1: reversed polarity ro 0b 3:0 reserved ro - downloaded from: http:///
lan9252 ds00001909a-page 168 ? 2015 microchip technology inc. table 11-13: auto-mdix enable and auto-mdix state bit functionality auto-mdix enable auto-mdix state mode 0 0 manual mode, no crossover 0 1 manual mode, crossover 1 0 auto-mdix mode 1 1 reserved (do not use this state) downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 169 lan9252 11.2.16.19 phy x cable length register (phy_cable_len_x) index (in decimal): 28 size: 16 bits bits description type default 15:12 cable length (cbln) this four bit value indicates the cable length. refer to section 11.2.12.2, "matched cable diagnostics," on page 139 for additional information on the usage of this field. note: this field indicates cable leng th for 100base-tx linked devices that do not have an open/short on the cable. to determine the open/short status of the cable, the phy x tdr patterns/delay control register (phy_tdr_pat_delay_x) and phy x tdr control/status register (phy_tdr_control_stat_x) must be used. cable length is not supported for 10base-t links. refer to section 11.2.12, "cable diagnostics," on page 136 for additional information. ro 0000b 11:0 reserved - write as 100000000000b, ignore on read r/w - downloaded from: http:///
lan9252 ds00001909a-page 170 ? 2015 microchip technology inc. 11.2.16.20 phy x interrupt source flag s register (phy_interrupt_source_x) this read-only register is used to determine to source of va rious phy interrupts. all interrupt source bits in this register are read-only and latch high upon detection of the corresponding interrupt (if enabled). a read of this register clears the interrupts. these interrupts are enabled or masked via the phy x interrupt mask register (phy_inter- rupt_mask_x) . index (decimal): 29 size: 16 bits bits description type default 15:9 reserved ro - 9 int9 this interrupt source bit indicates a link up (link status asserted). 0: not source of interrupt 1: link up (link status asserted) ro/lh 0b 8 int8 0: not source of interrupt 1: wake on lan (wol) event detected ro/lh 0b 7 int7 this interrupt source bit indicates when the energy on (energyon) bit of the phy x mode control/status r egister (phy_mode_control_sta- tus_x) has been set. 0: not source of interrupt 1: energyon generated ro/lh 0b 6 int6 this interrupt source bit indicates auto-negotiation is complete. 0: not source of interrupt 1: auto-negotia tion complete ro/lh 0b 5 int5 this interrupt source bit indicate s a remote fault has been detected. 0: not source of interrupt 1: remote fault detected ro/lh 0b 4 int4 this interrupt source bit indicates a link down (link status negated). 0: not source of interrupt 1: link down (link status negated) ro/lh 0b 3 int3 this interrupt source bit indicates an auto-negotiation lp acknowledge. 0: not source of interrupt 1: auto-negotiation lp acknowledge ro/lh 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 171 lan9252 2 int2 this interrupt source bit indicates a parallel detection fault. 0: not source of interrupt 1: parallel detection fault ro/lh 0b 1 int1 this interrupt source bit indicates an auto-negotiation page received. 0: not source of interrupt 1: auto-negotiation page received ro/lh 0b 0 reserved ro - bits description type default downloaded from: http:///
lan9252 ds00001909a-page 172 ? 2015 microchip technology inc. 11.2.16.21 phy x interrupt mask register (phy_interrupt_mask_x) this read/write register is used to enable or mask the various phy interrupts and is used in conjunction with the phy x interrupt source flags regist er (phy_interrupt_source_x) . index (decimal): 30 size: 16 bits bits description type default 15:10 reserved ro - 9 int9_mask this interrupt mask bit enables/masks the link up (link status asserted) inter- rupt. 0: interrupt source is masked 1: interrupt source is enabled r/w 0b 8 int8_mask this interrupt mask bit enabl es/masks the wol interrupt. 0: interrupt source is masked 1: interrupt source is enabled r/w 0b 7 int7_mask this interrupt mask bit enables /masks the energyon interrupt. 0: interrupt source is masked 1: interrupt source is enabled r/w 0b 6 int6_mask this interrupt mask bi t enables/masks the auto -negotiation interrupt. 0: interrupt source is masked 1: interrupt source is enabled r/w 0b 5 int5_mask this interrupt mask bi t enables/masks the remo te fault interrupt. 0: interrupt source is masked 1: interrupt source is enabled r/w 0b 4 int4_mask this interrupt mask bit en ables/masks the link down (link status negated) interrupt. 0: interrupt source is masked 1: interrupt source is enabled r/w 0b 3 int3_mask this interrupt mask bit enables/masks the auto-negotiation lp acknowledge interrupt. 0: interrupt source is masked 1: interrupt source is enabled r/w 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 173 lan9252 2 int2_mask this interrupt mask bit en ables/masks the parallel de tection fault interrupt. 0: interrupt source is masked 1: interrupt source is enabled r/w 0b 1 int1_mask this interrupt mask bit enables/masks the auto-negotiation page received interrupt. 0: interrupt source is masked 1: interrupt source is enabled r/w 0b 0 reserved ro - bits description type default downloaded from: http:///
lan9252 ds00001909a-page 174 ? 2015 microchip technology inc. 11.2.16.22 phy x special control/status register (phy_special_control_status_x) this read/write register is used to control and monitor various options of the phy. index (decimal): 31 size: 16 bits bits description type default 15:13 reserved ro - 12 autodone this bit indicates the status of the auto-negotiation on the phy. 0: auto-negotiation is not complete d, is disabled, or is not active 1: auto-negotiation is completed ro 0b 11:5 reserved - write as 00 00010b, ignore on read r/w 0000010b 4:2 speed indication this field indicates the current phy speed configuration. ro xxxb 1:0 reserved ro 0b state description 000 reserved 001 10base-t half-duplex 010 100base-tx half-duplex 011 reserved 100 reserved 101 10base-t full-duplex 110 100base-tx full-duplex 111 reserved downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 175 lan9252 mdio manageable device (mmd) registers the device mmd registers adhere to the ieee 802.3-2008 45.2 mdio interface registers specification. the mmd reg- isters are not memory mapped. these r egisters are accessed indirectly via the phy x mmd access control register (phy_mmd_access) and phy x mmd access address/data register (phy_mmd_addr_data) . the supported mmd device addresses are 3 (pcs), 7 (auto-negotiation), and 30 (vendor specific). table 11-14, "mmd registers" details the supported registers within each mmd device. table 11-14: mmd registers mmd device address (in decimal) index (in decimal) register name 3 (pcs) 5 phy x pcs mmd devices present 1 register (phy_pcs_mmd_pre- sent1_x) 6 phy x pcs mmd devices present 2 register (phy_pcs_mmd_pre- sent2_x) 32784 phy x wakeup control and status register (phy_wucsr_x) 32785 phy x wakeup filter configurat ion register a (phy_wuf_cfga_x) 32786 phy x wakeup filter configurat ion register b (phy_wuf_cfgb_x) 32801 phy x wakeup filter byte mask registers (phy_wuf_mask_x) 32802 32803 32804 32805 32806 32807 32808 32865 phy x mac receive address a register (phy_rx_addra_x) 32866 phy x mac receive address b register (phy_rx_addrb_x) 32867 phy x mac receive address c register (phy_rx_addrc_x) 7 (auto-negotiation) 5 phy x auto-negotiation mmd devices present 1 register (phy_an_mmd_present1_x) 6 phy x auto-negotiation mmd devices present 2 register (phy_an_mmd_present2_x) downloaded from: http:///
lan9252 ds00001909a-page 176 ? 2015 microchip technology inc. to read or write an mmd register, the following procedure must be observed: 1. write the phy x mmd access control register (phy_mmd_access) with 00b (address) for the mmd function field and the desired mmd device (3 for pcs, 7 for auto-negotiation) for the mmd device address (devad) field. 2. write the phy x mmd access address/data register (phy_mmd_addr_data) with the 16-bit address of the desired mmd register to read/write within the previous ly selected mmd device (pcs or auto-negotiation). 3. write the phy x mmd access control register (phy_mmd_access) with 01b (data) for the mmd function field and choose the previously selected mmd device (3 for pcs, 7 for auto-negotiation) for the mmd device address (devad) field. 4. if reading, read the phy x mmd access address/data register (phy_mmd_addr_data) , which contains the selected mmd register contents. if writing, write the phy x mmd access address/data register (phy_m- md_addr_data) with the register contents intended for the previously selected mmd register. unless otherwise specified, reserved fields must be written with zeros if the register is written. 30 (vendor specific) 2 phy x vendor specific mmd 1 device id 1 register (phy_vend_spec_mmd1_devid1_x) 3 phy x vendor specific mmd 1 device id 2 register (phy_vend_spec_mmd1_devid2_x) 5 phy x vendor specific mmd 1 devices present 1 register (phy_vend_spec_mmd1_present1_x) 6 phy x vendor specific mmd 1 devices present 2 register (phy_vend_spec_mmd1_present2_x) 8 phy x vendor specific mmd 1 status register (phy_vend_spec_mmd1_stat_x) 14 phy x vendor specific mmd 1 package id 1 register (phy_vend_spec_mmd1_pkg_id1_x) 15 phy x vendor specific mmd 1 package id 2 register (phy_vend_spec_mmd1_pkg_id2_x) table 11-14: mmd registers (continued) mmd device address (in decimal) index (in decimal) register name downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 177 lan9252 11.2.16.23 phy x pcs mmd devices present 1 register (phy_p cs_mmd_present1_x) index (in decimal): 3.5 size: 16 bits bits description type default 15:8 reserved ro - 7 auto-negotiation present 0 = auto-negotiation not present in package 1 = auto-negotiation present in package ro 1b 6 tc present 0 = tc not present in package 1 = tc present in package ro 0b 5 dte xs present 0 = dte xs not present in package 1 = dte xs present in package ro 0b 4 phy xs present 0 = phy xs not present in package 1 = phy xs present in package ro 0b 3 pcs present 0 = pcs not present in package 1 = pcs present in package ro 1b 2 wis present 0 = wis not present in package 1 = wis present in package ro 0b 1 pmd/pma present 0 = pmd/pma not present in package 1 = pmd/pma present in package ro 0b 0 clause 22 registers present 0 = clause 22 registers not present in package 1 = clause 22 registers present in package ro 0b downloaded from: http:///
lan9252 ds00001909a-page 178 ? 2015 microchip technology inc. 11.2.16.24 phy x pcs mmd devices present 2 register (phy_p cs_mmd_present2_x) index (in decimal): 3.6 size: 16 bits bits description type default 15 vendor specific device 2 present 0 = vendor specific device 2 not present in package 1 = vendor specific device 2 present in package ro 0b 14 vendor specific device 1 present 0 = vendor specific device 1 not present in package 1 = vendor specific device 1 present in package ro 1b 13 clause 22 extension present 0 = clause 22 extension not present in package 1 = clause 22 extension present in package ro 0b 12:0 reserved ro - downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 179 lan9252 11.2.16.25 phy x wakeup control and status register (phy_wucsr_x) note 17: register bits designated as nasr are reset when the phy reset is generated via the reset control reg- ister (reset_ctl) . the nasr designation is only applicable when the soft reset (phy_srst) bit of the phy x basic control regist er (phy_basic_control_x) is set. index (in decimal): 3.32784 size: 16 bits bits description type default 15:9 reserved ro - 8 wol configured this bit may be set by software after the wol registers are configured. this sticky bit (and all other w ol related register bits) is reset only via a power cycle or a pin reset, allowing software to skip programming of the wol regis- ters in response to a wol event. note: refer to section 11.2.9, "wake on lan (wol)," on page 132 for additional information. r/w/ nasr note 17 0b 7 perfect da frame received (pfda_fr) the mac sets this bit upon receiving a valid frame with a destination address that matches the physical address. r/wc/ nasr note 17 0b 6 remote wakeup frame received (wufr) the mac sets this bit upon receiving a valid remote wakeup frame. r/wc/ nasr note 17 0b 5 magic packet received (mpr) the mac sets this bit upon receiving a valid magic packet. r/wc/ nasr note 17 0b 4 broadcast frame received (bcast_fr) the mac sets this bit upon receiving a valid broadcast frame. r/wc/ nasr note 17 0b 3 perfect da wakeup enable (pfda_en) when set, remote wakeup mode is enabled and the mac is capable of wak- ing up on receipt of a frame with a de stination address that matches the physical address of the device. the physical address is stored in the phy x mac receive address a register (phy_rx_addra_x) , phy x mac receive address b register (phy_rx_addrb_x) and phy x mac receive address c register (phy_rx_addrc_x) . r/w/ nasr note 17 0b 2 wakeup frame enable (wuen) when set, remote wakeup mode is enabled and the mac is capable of detecting wakeup frames as programmed in the wakeup filter. r/w/ nasr note 17 0b 1 magic packet enable (mpen) when set, magic packet wakeup mode is enabled. r/w/ nasr note 17 0b 0 broadcast wakeup enable (bcst_en) when set, remote wakeup mode is enabled and the mac is capable of wak- ing up from a broadcast frame. r/w/ nasr note 17 0b downloaded from: http:///
lan9252 ds00001909a-page 180 ? 2015 microchip technology inc. 11.2.16.26 phy x wakeup filter configuration register a (phy_wuf_cfga_x) note 18: register bits designated as nasr are reset when the phy reset is generated via the reset control reg- ister (reset_ctl) . the nasr designation is only applicable when the soft reset (phy_srst) bit of the phy x basic control regist er (phy_basic_control_x) is set. index (in decimal): 3.32785 size: 16 bits bits description type default 15 filter enable 0 = filter disabled 1 = filter enabled r/w/ nasr note 18 0b 14 filter triggered 0 = filter not triggered 1 = filter triggered r/wc/ nasr note 18 0b 13:11 reserved ro - 10 address match enable when set, the destination address must match the programmed address. when cleared, any unicast packet is accepted. refer to section 11.2.9.4, "wakeup frame detection," on page 133 for additional information. r/w/ nasr note 18 0b 9 filter any multicast enable when set, any multicast packet other than a broadcast will cause an address match. refer to section 11.2.9.4, "wakeup frame detection," on page 133 for additional information. note: this bit has priority over bit 10 of this register. r/w/ nasr note 18 0b 8 filter broadcast enable when set, any broadcast frame will cause an address match. refer to sec- tion 11.2.9.4, "wakeup frame detection," on page 133 for additional informa- tion.note: this bit has priority over bit 10 of this register. r/w/ nasr note 18 0b 7:0 filter pattern offset specifies the offset of the first by te in the frame on which crc checking begins for wakeup frame recognition. offset 0 is the first byte of the incom- ing frames destination address. r/w/ nasr note 18 00h downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 181 lan9252 11.2.16.27 phy x wakeup filter configuration register b (phy_wuf_cfgb_x) note 19: register bits designated as nasr are reset when the phy reset is generated via the reset control reg- ister (reset_ctl) . the nasr designation is only applicable when the soft reset (phy_srst) bit of the phy x basic control regist er (phy_basic_control_x) is set. index (in decimal): 3.32786 size: 16 bits bits description type default 15:0 filter crc-16 this field specifies the expe cted 16-bit crc value for the filter that should be obtained by using the pattern offset and the byte mask programmed for the fil- ter. this value is compared against the crc calculated on the incoming frame, and a match indicates t he reception of a wakeup frame. r/w/ nasr note 19 0000h downloaded from: http:///
lan9252 ds00001909a-page 182 ? 2015 microchip technology inc. 11.2.16.28 phy x wakeup filter by te mask registers (phy_wuf_mask_x) index (in decimal): 3.32801 size: 16 bits bits description type default 15:0 wakeup filter byte mask [127:112] r/w/ nasr note 20 0000h index (in decimal): 3.32802 size: 16 bits bits description type default 15:0 wakeup filter byte mask [111:96] r/w/ nasr note 20 0000h index (in decimal): 3.32803 size: 16 bits bits description type default 15:0 wakeup filter byte mask [95:80] r/w/ nasr note 20 0000h index (in decimal): 3.32804 size: 16 bits bits description type default 15:0 wakeup filter byte mask [79:64] r/w/ nasr note 20 0000h downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 183 lan9252 note 20: register bits designated as nasr are reset when the phy reset is generated via the reset control reg- ister (reset_ctl) . the nasr designation is only applicable when the soft reset (phy_srst) bit of the phy x basic control regist er (phy_basic_control_x) is set. index (in decimal): 3.32805 size: 16 bits bits description type default 15:0 wakeup filter byte mask [63:48] r/w/ nasr note 20 0000h index (in decimal): 3.32806 size: 16 bits bits description type default 15:0 wakeup filter byte mask [47:32] r/w/ nasr note 20 0000h index (in decimal): 3.32807 size: 16 bits bits description type default 15:0 wakeup filter byte mask [31:16] r/w/ nasr note 20 0000h index (in decimal): 3.32808 size: 16 bits bits description type default 15:0 wakeup filter byte mask [15:0] r/w/ nasr note 20 0000h downloaded from: http:///
lan9252 ds00001909a-page 184 ? 2015 microchip technology inc. 11.2.16.29 phy x mac receive addr ess a register (phy_rx_addra_x) note 21: register bits designated as nasr are reset when the phy reset is generated via the reset control reg- ister (reset_ctl) . the nasr designation is only applicable when the soft reset (phy_srst) bit of the phy x basic control regist er (phy_basic_control_x) is set. index (in decimal): 3.32865 size: 16 bits bits description type default 15:0 physical address [47:32] r/w/ nasr note 21 ffffh downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 185 lan9252 11.2.16.30 phy x mac receive addr ess b register (phy_rx_addrb_x) note 22: register bits designated as nasr are reset when the phy reset is generated via the reset control reg- ister (reset_ctl) . the nasr designation is only applicable when the soft reset (phy_srst) bit of the phy x basic control regist er (phy_basic_control_x) is set. index (in decimal): 3.32866 size: 16 bits bits description type default 15:0 physical address [31:16] r/w/ nasr note 22 ffffh downloaded from: http:///
lan9252 ds00001909a-page 186 ? 2015 microchip technology inc. 11.2.16.31 phy x mac receive addr ess c register (phy_rx_addrc_x) note 23: register bits designated as nasr are reset when the phy reset is generated via the reset control reg- ister (reset_ctl) . the nasr designation is only applicable when the soft reset (phy_srst) bit of the phy x basic control regist er (phy_basic_control_x) is set. index (in decimal): 3.32867 size: 16 bits bits description type default 15:0 physical address [15:0] r/w/ nasr note 23 ffffh downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 187 lan9252 11.2.16.32 phy x auto-negotiation mmd devices present 1 register (phy_an_mmd_present1_x) index (in decimal): 7.5 size: 16 bits bits description type default 15:8 reserved ro - 7 auto-negotiation present 0 = auto-negotiation not present in package 1 = auto-negotiation present in package ro 1b 6 tc present 0 = tc not present in package 1 = tc present in package ro 0b 5 dte xs present 0 = dte xs not present in package 1 = dte xs present in package ro 0b 4 phy xs present 0 = phy xs not present in package 1 = phy xs present in package ro 0b 3 pcs present 0 = pcs not present in package 1 = pcs present in package ro 1b 2 wis present 0 = wis not present in package 1 = wis present in package ro 0b 1 pmd/pma present 0 = pmd/pma not present in package 1 = pmd/pma present in package ro 0b 0 clause 22 registers present 0 = clause 22 registers not present in package 1 = clause 22 registers present in package ro 0b downloaded from: http:///
lan9252 ds00001909a-page 188 ? 2015 microchip technology inc. 11.2.16.33 phy x auto-negotiation mmd devices present 2 register (phy_an_mmd_present2_x) index (in decimal): 7.6 size: 16 bits bits description type default 15 vendor specific device 2 present 0 = vendor specific device 2 not present in package 1 = vendor specific device 2 present in package ro 0b 14 vendor specific device 1 present 0 = vendor specific device 1 not present in package 1 = vendor specific device 1 present in package ro 1b 13 clause 22 extension present 0 = clause 22 extension not present in package 1 = clause 22 extension present in package ro 0b 12:0 reserved ro - downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 189 lan9252 11.2.16.34 phy x vendor specific mmd 1 device id 1 register (phy_v end_spec_mmd1_ devid1_x) index (in decimal): 30.2 size: 16 bits bits description type default 15:0 reserved ro 0000h downloaded from: http:///
lan9252 ds00001909a-page 190 ? 2015 microchip technology inc. 11.2.16.35 phy x vendor specific mmd 1 device id 2 register (phy_vend_spec_mmd1_devid2_x) index (in decimal): 30.3 size: 16 bits bits description type default 15:0 reserved ro 0000h downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 191 lan9252 11.2.16.36 phy x vendor specific mmd 1 devices present 1 register (phy_vend_spec_mmd1_present1_x) index (in decimal): 30.5 size: 16 bits bits description type default 15:8 reserved ro - 7 auto-negotiation present 0 = auto-negotiation not present in package 1 = auto-negotiation present in package ro 1b 6 tc present 0 = tc not present in package 1 = tc present in package ro 0b 5 dte xs present 0 = dte xs not present in package 1 = dte xs present in package ro 0b 4 phy xs present 0 = phy xs not present in package 1 = phy xs present in package ro 0b 3 pcs present 0 = pcs not present in package 1 = pcs present in package ro 1b 2 wis present 0 = wis not present in package 1 = wis present in package ro 0b 1 pmd/pma present 0 = pmd/pma not present in package 1 = pmd/pma present in package ro 0b 0 clause 22 registers present 0 = clause 22 registers not present in package 1 = clause 22 registers present in package ro 0b downloaded from: http:///
lan9252 ds00001909a-page 192 ? 2015 microchip technology inc. 11.2.16.37 phy x vendor specific mmd 1 devices present 2 register (phy_vend_spec_mmd1_present2_x) index (in decimal): 30.6 size: 16 bits bits description type default 15 vendor specific device 2 present 0 = vendor specific device 2 not present in package 1 = vendor specific device 2 present in package ro 0b 14 vendor specific device 1 present 0 = vendor specific device 1 not present in package 1 = vendor specific device 1 present in package ro 1b 13 clause 22 extension present 0 = clause 22 extension not present in package 1 = clause 22 extension present in package ro 0b 12:0 reserved ro - downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 193 lan9252 11.2.16.38 phy x vendor specific mmd 1 status register (phy_vend_spec_mmd1_stat_x) index (in decimal): 30.8 size: 16 bits bits description type default 15:14 device present 00 = no device responding at this address 01 = no device responding at this address 10 = device responding at this address 11 = no device responding at this address ro 10b 13:0 reserved ro - downloaded from: http:///
lan9252 ds00001909a-page 194 ? 2015 microchip technology inc. 11.2.16.39 phy x vendor specific mmd 1 package id 1 register (phy_vend_spec_ mmd1_pkg_id1_x) index (in decimal): 30.14 size: 16 bits bits description type default 15:0 reserved ro 0000h downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 195 lan9252 11.2.16.40 phy x vendor specific mmd 1 package id 2 register (phy_vend_spec_mmd1_pkg_id2_x) . index (in decimal): 30.15 size: 16 bits bits description type default 15:0 reserved ro 0000h downloaded from: http:///
lan9252 ds00001909a-page 196 ? 2015 microchip technology inc. 12.0 ethercat 12.1 ethercat functional overview the ethercat module implements a 3 port ethercat slave cont roller with 4k bytes of dual port memory (dpram), 4 syncmanagers, 3 fieldbus memory management units (fmmus) and a 64-bit distributed clock. each port receives an ethernet frame, performs frame checking and forwards it to the next port. time stamps of received frames are generated when they are receiv ed. the loop-back function of each port forwards ethernet frames to the next logical port if there is either no link at a port, or if th e port is not available, or if the loop is closed for that port . the loop-back function of port 0 forwards the frames to the et hercat processing unit. the lo op settings can be controlled by the ethercat master. packets are forwarded in the following order: po rt 0->ethercat processing unit->port 1->port 2. the ethercat processing unit (epu) receives, analyses and processes the ethercat data stream. the main purpose of the ethercat processing unit is to enable and coordinate access to the inte rnal registers and the memory space of the esc, which can be addressed both from the ethercat master and from th e local application. data exchange between master and slave application is comparable to a dual-ported memory (process memory), enhanced by special functions e.g. for consistency checking (syncmanager) and data mapping (fmmu). each fmmu performs the task of bitwis e mapping of logical ethe rcat system addresses to physical addresses of the device. syncmanagers are responsible for cons istent data exchange and mailbox co mmunication between ethercat master and slaves. each syncmanager's direction and mode of operation is configured by t he ethercat master. two modes of operation are available: buffered mode or mailbox mode. in the buffered m ode, both the local microcontroller and ethercat master can write to the device concurrently. the buffer within the lan9252 will always contain the latest data. if newer data arrives before the old data can be read out, the old data will be dropped. in mailbox mode, access to the buffer by the local microcontroller and the ethercat master is performed using handshakes, guaranteeing that no data will be dropped. distributed clocks (dc) allow for precisely synchronized ge neration of output signals and input sampling, as well as time stamp generation of events. the ethercat chapter consists of the following main sections: section 12.2, "distributed clocks," on page 197 section 12.3, "pdi selection and configuration," on page 198 section 12.4, "digital i/o pdi," on page 198 section 12.5, "host interface pdi," on page 200 section 12.6, "gpios," on page 201 section 12.7, "user ram," on page 201 section 12.8, "eeprom config urable registers," on page 201 section 12.9, "port interfaces," on page 202 section 12.10, "leds," on page 208 section 12.11, "ethercat csr and process data ram access," on page 208 section 12.12, "ethercat reset," on page 213 section 12.13, "ethercat csr and process data ram a ccess registers (directly addressable)," on page 214 section 12.14, "ethercat core csr regist ers (indirectly addressable)," on page 223 refer to figure 2-2: internal block diagram on page 9 for an overview of the interconnection of the ethercat module within the device. downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 197 lan9252 12.2 distributed clocks the device supports 64-bit di stributed clocks as detailed in the following sub-sections. 12.2.1 sync/latch pin multiplexing the ethercat core provides two input pins ( latch0 and latch1 ) which are used for time stamping of external events. both rising edge and falling edge time stamps are recorded. these pins are shared with the sync0 and sync1 output pins, respectively, which are used to indicate the occurrence of time events. the functions of the sync0 / latch0 and sync1 / latch1 pins are determined by the sync0/latch0 configuration and sync1/latch1 configuration bits of the sync/latch pdi conf iguration register , respectively. when set for sync0 / sync1 functionality, the output type (push-pull vs. open drain/source) and output polarity are determined by the sync0 output driver/polarity and sync1 output driver/polarity bits of the sync/latch pdi config- uration register . 12.2.2 sync irq mapping the sync0 and sync1 states can be mapped into the state of dc sync0 and state of dc sync1 bits of the al event request register , respectively. the mapping of the sync0 and sync1 states is enabled by the sync0 map and sync1 map bits of the sync/latch pdi configuration register , respectively. 12.2.3 sync pulse length the sync0 and sync1 pulse length is controlled via the pulse length of syncsignals register . the pulse length of syncsignals register is initialized from the co ntents of eeprom. refer to section 12.8, "eeprom configurable reg- isters," on page 201 for additional information. 12.2.4 sync/latch i/o timing requirements this section specifies the sync0 / latch0 and sync1 / latch1 input and output timings. note: the sync/latch pdi configuration register is initialized from the co ntents of eeprom. refer to section 12.8, "eeprom configurabl e registers," on page 201 for additional information. note: the sync/latch pdi configuration register is initialized from the co ntents of eeprom. refer to section 12.8, "eeprom configurabl e registers," on page 201 for additional information. figure 12-1: ethercat sync/latch timing diagram table 12-1: ethercat sync/latch timing values symbol description min typ max units t dc_latch time between latch0 or latch1 events 15 - - ns t dc_sync_jitter sync0 or sync1 output jitter - - 15 ns latch0/1 sync0/1 t dc_latch t dc_latch t dc_sync_jitter t dc_sync_jitter o u t p u t e v e n t t i m e downloaded from: http:///
lan9252 ds00001909a-page 198 ? 2015 microchip technology inc. 12.3 pdi selection and configuration the process data interface (pdi) used by the device is indicated via the pdi control register . the available pdis are: 04h: digital i/o pdi 80h-8dh: host interface pdi (spi, hbi multiplexed/indexed 1/2 phase 8/16-bit) note: the pdi control register can be configured via eeprom. refer to section 12.8, "eepr om configurable registers," on page 201 for additional information. the host interface pdi is used to support hbi and spi modes, as described in section 14.0, "chip mode configuration," on page 296 . the configuration of the enabled pdi is controlled via the pdi configuration register and extended pdi configuration register . the definition of these registers depends on the sele cted mode of operation. however, only one register set exists. 12.4 digital i/o pdi the digital i/o pdi provides 16 configurable digital i/os ( digio[15:0] ) to be used for simp le systems without a host controller. the digital i/o output data register is used to control the output values, while the digital i/o input data reg- ister is used to read the input values. each 2-bit pair of the digital i/os is configurable as an input or output. the direction is selected by the extended pdi configuration register , which is configured via eeprom (refer to section 12.8, "eeprom configurable registers," on page 201 for additional information). the di gital i/os can also be configured to bi-directional mode, where the outputs are driven and latched externally and then released so that the input data can be sampled. bi-directional operation is selected via the unidirectional/bidirectional mode bit of the pdi configuration register . the pdi configuration register is initialized from th e contents of eeprom. 12.4.1 output watchdog behavior the watchdog control of the digital output s can be configured to specify if the expiration of the syncmanager watchdog will have an immediate effect on the i/o signals (output rese t immediately after watchdog timeout) or if the effect is delayed until the next output ev ent (output reset with next output event). the choice is determined by the watchdog behavior bit of the pdi configuration register . the pdi configuration register is initialized from the contents of eeprom. refer to section 12.8, "eeprom configurable registers," on page 201 for additional information. 12.4.2 oe_ext output watchdog behavior for external watchdog implementations, the wd_trig (watchdog trigger) pin can be us ed. a pulse is generated if the syncmanager watchdog is triggered. in this case, the internal syncmanager watchdog should be disabled, and the external watchdog may use the oe_ext pin to reset the i/o signals if the watchdog is expired. the outvalid mode bit of the pdi configuration register controls if wd_trig is mapped onto the outvalid pin. the pdi configuration register is initialized from the contents of eeprom. since there is a dedicated wd_trig pin, this bit is normally set to 0 in the eeprom. 12.4.3 input data sampling digital inputs can be configured to be sampled in four ways, at the start of each ethernet frame, at the rising edge of the latch_in pin, at distributed clocks sync0 events or at distributed clocks sync1 events. the choice of sampling mode is determined by the input data sample selection bits of the pdi configuration register . the pdi configuration register is initialized from the contents of eeprom. 12.4.4 output data updating digital outputs can be configured to be update four ways, at the end of each ethernet frame, with distributed clocks sync0 events, with di stributed clocks sync1 events or at the end of an ethercat frame which triggered the process data watchdog. the choice of sampling mode is determined by the output data sample selection bits of the pdi con- figuration register . the pdi configuration register is initialized from the contents of eeprom. 12.4.5 outvalid polarity the output polarity of the outvalid pin is determined by the outvalid polarity bit of the pdi configuration register . the pdi configuration register is initialized from the contents of eeprom. downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 199 lan9252 12.4.6 digital i/o timing requirements this section specifies the digio[15:0] , latch_in and sof input and output timings. figure 12-2: ethercat digital i/o input timing diagram figure 12-3: ethercat digital i/o output timing diagram sof digio[15:0] t sof t sofdatah t sofdatav latch_in t latchin t latchindelay t indatalatchs t indatalatchh sync0/1 t indatasyncs t indatasynch digio[15:0] outvalid t outdatas t outvaliddelay t outvalid wd_trig t wd_trig t wd_trigdata oe_ext t oe_extdata eof t eof t eofdata sync0/1 t syncdata downloaded from: http:///
lan9252 ds00001909a-page 200 ? 2015 microchip technology inc. 12.5 host interface pdi the host interface pdi is used for systems with a host contro ller that use either a hbi or spi chip-level host interface. the values in the pdi configuration register and the extended pdi configuration register reflect the value from eeprom. the value in the pdi configuration register is used for host interface modes to configure the hbi. the value in the extended pdi configuration register is used if gpios are enabled (spi w/gpio). the pdi configuration register and extended pdi configuration register are initialized from the contents of the eeprom. refer to section 12.8, "eeprom configurable registers," on page 201 for additional information. figure 12-4: ethercat digital i/o bi-directional timing diagram table 12-2: ethercat digital i/o timing values symbol description min typ max units t indatasyncs input data setup to sync0/1 rising 10 - - ns t indatasynch input data hold from sync0/1 rising 0 - - ns t indatalatchs input data setup to latch_in rising 8 - - ns t indatalatchh input data hold from latch_in rising 4 - - ns t latchin latch_in high time 8 - - ns t latchindelay time between consecutive input events 440 - - ns t sof sof high time 35 - 45 ns t sofdatav input data valid after sof active, so that input data can be read in the same frame --1 . 2 ? s t sofdatah input data hold after sof active, so that input data can be read in the same frame 1.6 - - ? s t outdatas output data setup to outvalid rising 65 - - ns t outdatah output data hold from outvalid falling 65 - - ns t outvalid outvalid high time 75 - 85 ns t outvaliddelay time between consecutive output events 320 - - ns t eof eof high time 35 - 45 ns t eofdata output data valid after eof --3 5n s t wd_trig wd_trig high time 35 - 45 ns t wd_trigdata output data valid after wd_trig --3 5n s t syncdata output data valid after sync0/1 --2 5n s t oe_extdata oe_ext to data low 0 - 15 ns t bidirdelay time between consecutive input or output events 440 - - ns digio[15:0] outvalid t outdatas t outvalid output data input data t outdatah input data input events input events allowed input events allowed no input events allowed t bidirdelay t bidirdelay downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 201 lan9252 12.6 gpios the ethercat core provides 16 general purpose inputs ( gpi[15:0] ) and 16 general purpose outputs ( gpo[15:0] ) the general purpose output register is used to control the output value. the general purpose input register is used to read the input value. each 2-bit pair is configurable as input, push-pull output or open-drain output. the direction and buffer type are deter- mined by the extended pdi configuration register . bits 7:0 control the direction of t he pairs (bit 0 for gpio[1:0], bit 1 for gpio[3:2], etc.). a value of 1 selects the output direction. bits 15:8 control the output type (bit 8 for gpio[1:0], bit 9 for gpio[3:2], etc.). a value of 1 selects the open-drain. the extended pdi configuration register is initialized from the contents of the eeprom. refer to section 12.8, "eeprom configurable registers," on page 201 for additional infor- mation. 12.7 user ram a 128 byte user ram is located at 0f80h-0fffh . the default values within this ram are undefined for all addresses. 12.8 eeprom configurable registers the following registers are configurable via eeprom. refer to the corresponding register definition for details on each bit function. note: when gpios are not available due to chip configuration, the general purpose output register remains r/ w, but has no effect. when gpios are not available due to chip configuration, the general purpose input register will return zeros. note: the extended pdi configuration register is also used for the digital i/o pdi direction. however, gpios are not used during digital i/o mode. note: reserved bits must be written as 0 unless otherwise noted. table 12-3: ethercat core eeprom configurable registers register bits eeprom word / [bits] pdi control register ( 0140h ) [7:0] process data interface 0 / [7:0] esc configuration register ( 0141h ) [7] (unused) 0 / [15] [6] enhanced link port 2 0 / [14] [5] enhanced link port 1 0 / [13] [4] enhanced link port 0 0 / [12] [3] distributed clocks latch in unit note: bit 3 is not set by eeprom - [2] distributed clocks sync out unit note: bit 2 is not set by eeprom - [1] enhanced link detection all ports 0 / [9] [0] device emulation (control of al status register ) 0 / [8] downloaded from: http:///
lan9252 ds00001909a-page 202 ? 2015 microchip technology inc. 12.9 port interfaces 12.9.1 ports 0 and 2 (internal phy a or external mii) port 0 of the ethercat slave is connected to internal phy a when chip_mode_strap[1:0] is not equal to 11b (2 port mode or 3 port downstream mode). port 0 is connected to the mii pins when chip_mode_strap[1:0] is equal to 11b (3 port upstream mode). port 2 of the ethercat slave is c onnected to internal phy a when chip_mode_strap[1:0] is equal to 11b (3 port upstream mode). port 2 is c onnected to the mii pins when chip_mode_strap[1:0] is equal to 10b (3 port downstream mode). pdi configuration register ( 0150h ) digital i/o mode [7:6] output data sample selection 1 / [7:6] [5:4] input data sample selection 1 / [5:4] [3] watchdog behavior 1 / [3] [2] unidirectional/bidirectional mode 1 / [2] [1] outvalid mode 1 / [1] [0] outvalid polarity 1 / [0] pdi configuration register ( 0150h ) hbi mode [7] hbi ale qualification 1 / [7] [6] hbi read/write mode 1 / [6] [5] hbi chip select polarity 1 / [5] [4] hbi read, read/write polarity 1 / [4] [3] hbi write, enable polarity 1 / [3] [2] hbi ale polarity 1 / [2] [1:0] reserved (unused) 1 / [1:0] sync/latch pdi configuration register ( 0151h ) [7] sync1 map 1 / [15] [6] sync1/latch1 configuration 1 / [14] [5:4] sync1 output driver/polarity 1 / [13:12] [3] sync0 map 1 / [11] [2] sync0/latch0 configuration 1 / [10] [1:0] sync0 output driver/polarity 1 / [9:8] pulse length of syncsignals register ( 0982h-0983h ) [15:0] pulse length of syncsignals 2 / [15:0] extended pdi configuration register ( 0152h-0153h ) digital i/o mode [15:8] reserved 3 / [15:8] [7:0] i/o 15-0 direction 3 / [7:0] extended pdi configuration register ( 0152h-0153h ) spi mode [15:8] i/o 15-0 buffer type 3 / [15:8] [7:0] i/o 15-0 direction 3 / [7:0] configured station alias register ( 0012h-0013h ) [15:0] configured station alias address 4 / [15:0] mii management control/status register ( 0510h-0511h ) [2] mi link detection 5 / [15] asic configuration register ( 0142h-0143h ) [15] mi link detection [14:8] reserved 5 / [14:8] [7] mi write gigabit register 9 enable 5 / [7] [6:0] reserved 5 / [6:0] reserved register ( 0144h-0145h ) [15:0] reserved 6 / [15:0] table 12-3: ethercat core eeprom configurable registers register bits eeprom word / [bits] downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 203 lan9252 12.9.1.1 external mi i phy connection an external phy is connected to the mii port as shown in figure 12-5 . the clock source for the ethernet phy and the ethercat slave must be the same. a 25 mhz output ( mii_clk25 ) is provided to be used as the reference clock for the phy. tx_clk from the phy is not connected since the ether cat slave does not incorporate a tx fifo. the tx signals from the ethercat slave may be delayed with respect to the cl k25 output by using tx shift compensation so that they align properly as if they were driven by the phys tx_clk. mii timing is described in section 12.9.7, "external phy timing" . the ethernet phy should be connected to the ethercat slave rst# pin so that the phy is held in reset until the eth- ercat slave is ready. otherwise, the far end link partner would detect valid link signals from the phy and would open its port assuming that the local ethercat slave was ready. the mii_mdc and mii_mdio signals are connected between the ethercat slave and the phy. mii_mdio requires an external pull-up. the management address of the external phy must be set to 0 when chip_mode_strap[1:0] is equal to 11b (3 port upstream mode) and to 2 when chip_mode_strap[1:0] is equal to 10b (3 port downstream mode). link_status from the phy is an led out put which indicates that a 100 mbit/s, full duplex link is active. the polarity of the mii_link input of the ethercat slave is configurable. the col and crs outputs from the phy are not connec ted since ethercat operates in full-duplex mode. the tx_er input to the phy is tied to system ground since the ethercat slave never generates transmit errors. 12.9.1.2 back-to-back connection two ethercat slave devices can be connected using a back-to-back mii connection as shown in figure 12-6 . one device is placed in 3 port upstream mode and the other in 3 port downstream mode. the clock sources of each ethercat slave may be different. the 25 mhz output ( mii_clk25 ) is provided to be used as the rx_clk input to the other device. the tx signals from each ethercat slave may be delayed with respect to the clk25 output by using tx shift compensation so that they align properly to meet the rx timing requirement of the other device. back-to-back mii timing is described in section 12.9.7, "external phy timing" . the mii_rxer signals are not used since the ethercat slaves never generate errors. the mii_mdio and mii_mdc signals are not used since neither device contains a phy register set. the mii_mdio pins require (separate) pull-ups so that a high va lue is returned when phy register reads are attempted. figure 12-5: ethercat external phy connection 0 or 2 25 mhz 0 ns 10 ns20 ns 30 ns vddio lan9252 mii_clk25 mii_link mii_rxclk mii_rxdv mii_rxd[3:0] mii_rxer mii_txen mii_txd[3:0] mii_mdio mii_mdc osci osco tx shift configuration rst# phy clk25 link_status rx_clk rx_dv rx_d[3:0] rx_er tx_clk tx_en tx_d[3:0] tx_er col crs mdio mdc phy_addr reset# downloaded from: http:///
lan9252 ds00001909a-page 204 ? 2015 microchip technology inc. mii_link may be tied active, if the two ethercat slaves are released from reset at about the same time. otherwise, mii_link can be used to indicate to the partner that the device is not ready. 12.9.1.3 2 port operation when configured for two port mode ( chip_mode_strap[1:0] equal to 00b), port 2 is disabled. the port status is also shown in the port 2 configuration bits of the port descriptor register and is set to a 01b (not configured) when the device is configured for two port operation. 12.9.2 port 1 (internal phy b) port 1 of the ethercat core is always connected to internal phy b. 12.9.3 phy configuration by default, the internal phys are configured for 100mbps, full-duplex operation. auto-negotiation is enable for 100base-tx mode and disable for 100base-fx mode. the ether cat core will also check and update the configura- tion if necessary. by default, the external phy is configured for 100mbps, full-duplex operation with auto-negotiation enabled. the eth- ercat core will check and update the configuration if necessary. 12.9.4 phy link status the link status originates from the phy s link signal (internal or external). the ethercat core also checks the phy sta- tus to determine a proper link. by cyclically polling the ph ys, it checks that auto-negotia tion registers are configure properly, if a link is established, if au to-negotiation has finished successfully and if the link partner also used auto-nego- tiation. link checking through the mii manag ement interface (mi) is enabled via eeprom an d reflected in the mii management control/status register . figure 12-6: ethercat back-to-back mii connection note: mi link detection is disabled un til the device is successfully configured from the eeprom. the eeprom setting for mi link detection is only taken at the first eeprom loading after power-on or reset. changing the eeprom and manually reloading it w ill not affect the mi link detection enable status, even if the eeprom could not be read initially. 25 mhz 10 ns20 ns vddio 25 mhz 10 ns 20 ns vddio towards master towards other salves lan9252 mii_clk25 mii_link mii_rxclk mii_rxdv mii_rxd[3:0] mii_rxer mii_txen mii_txd[3:0] mii_mdio mii_mdc osciosco tx shift configuration (downstream mode) rst# lan9252 mii_clk25 mii_link mii_rxclk mii_rxdv mii_rxd[3:0] mii_rxer mii_txen mii_txd[3:0] mii_mdio mii_mdc osci osco tx shift configuration (upstream mode) rst# downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 205 lan9252 as shown in table 12-3, "ethercat core eepr om configurable registers" , bit 7 of the asic configuration register is used to enable writes to phy register 9 for phys which use this register per ieee 802.3. 12.9.4.1 mi link detection a nd configuration state machine the mi link detection and configuratio n state machine operates as follows: check that auto-negotiation is enabled check that only 100base-x full-duplex is advertised check that 1000base-t is not advertised check that auto-negotiation is completed check that link partner is 100base-x full-duplex otherwise, set the registers as needed and restart auto-negotiation 12.9.5 enhanced link detection the ethercat core supports the enhanced link detection f eature with the enable is controlled by the eeprom. with this, the ethercat core will disconnect a link if at least 32 rx errors (rx_er) occur in a fixed interval of time (~10 us). refer to section 12.8, "eeprom configur able registers," on page 201 for additional information. 12.9.6 100base-fx support since 100base-fx operation does not provide support for au to-negotiation, special cons ideration is required for mi and enhanced link detection operation. mii link detection when any port is set for 100base-fx opera tion, mi link detection mu st be disabled by mainta ining bit 2 of the mii man- agement control/status register low. enhanced link detection enhanced link detection may still be enabled. if enhanced link de tection detects an error condition, it will still attempt to restart auto-negotiation. since this would have no effect, the internal phy is also reset. a system that uses an external 100base-fx phy must implement the logic described in the enhanced fx link detec- tion section of the beckhoff phy selection guide to detect the restart auto-negotiation command and reset the external phy and reset / disable the external transceiver. downloaded from: http:///
lan9252 ds00001909a-page 206 ? 2015 microchip technology inc. 12.9.7 external phy timing since the ethercat core does not use the phy transmit clock, proper timing must be ensured based on the common 25 mhz reference clock (which is output to the external phy via the mii_clk25 pin). to aid in this, the ethercat core has the tx shift feature enabled. this feature can delay th e generation of the transmit si gnals from the ethercat core by 0ns, 10ns, 20ns or 30ns. this value is manually set using tx_shift_strap[1:0] . 12.9.7.1 mii connection timing the mii interface tx and rx timing is as follows: note 1: timing is designed for a system load between 10 pf and 25 pf. note 2: assumes tx shift value of 2, add 10 ns for each increment of tx shift (shift values of 3, 0, and 1 in order). figure 12-7: mii tx timing table 12-4: mii tx timing values symbol description min max units notes t clkp mii_clk25 period 40 - ns t clkh mii_clk25 high time t clkp * 0.45 t clkp * 0.55 ns t clkl mii_clk25 low time t clkp * 0.45 t clkp * 0.55 ns t val mii_txd[3:0] , mii_txen output valid from rising edge of mii_clk25 note 2 - 10.0 ns note 1 t hold mii_txd[3:0] , mii_txen output hold from rising edge of mii_clk25 note 2 0-n s note 1 mii_clk25 mii_txd[3:0] mii_txen t clkh t clkl t clkp t val t hold (output) t val t val t hold downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 207 lan9252 note 3: timing is designed for a system load between 10 pf and 25 pf. 12.9.7.2 back-to -back mii connection timing with the previously listed mii tx and rx timings, back-to- back connections should use a tx shift value of 3 or 0. figure 12-8: mii rx timing table 12-5: mii rx timing values symbol description min max units notes t clkp mii_rxclk period 40 - ns t clkh mii_rxclk high time t clkp * 0.4 t clkp * 0.6 ns t clkl mii_rxclk low time t clkp * 0.4 t clkp * 0.6 ns t su mii_rxd[3:0] , mii_rxer , mii_rxdv setup time to rising edge of mii_rxclk 5.0 - ns note 3 t hold mii_rxd[3:0] , mii_rxer , mii_rxdv hold time after rising edge of mii_rxclk 6.0 - ns note 3 mii_rxclk t su mii_rxd[3:0], mii_rxer mii_rxdv t clkh t clkl t clkp t hold t su t hold t hold t su (input) t hold downloaded from: http:///
lan9252 ds00001909a-page 208 ? 2015 microchip technology inc. 12.9.7.3 management interface timing the mii_mdio and mii_mdc timing is follows: 12.10 leds the device includes one run led ( runled ) and a link / activity led per port ( linkactled[0:2] ). the led pin polar- ity is determined based on the corresponding led polarity strap. the pin outputs are open drain or open source. note: the led pins for port 0 and port 2 are not swapped based on the chip mode. the ethercat core configuration provides for direct control of the run led via the run led override register . all led outputs may be disabled (un-driven) by setting the led_dis bit in the power management control register (pmt_ctrl) . 12.11 ethercat csr and process data ram access the ethercat csrs provide register level access to the va rious parameters of the ethercat core. ethercat related registers can be classified into two main categories ba sed upon their method of access: direct and indirect. the directly accessible ethercat registers are part of the main system csrs and are detailed in section 12.13, "eth- ercat csr and process data ram access regist ers (directly addressable)," on page 214 . these registers provide data/command registers (for access to th e indirect ethercat core registers). the indirectly accessible ethercat core registers reside within the ethercat core and must be accessed indirectly via the ethercat csr interface data register (ecat_csr_data) and ethercat csr interface command register (ecat_csr_cmd) . the indirectly accessible ether cat core csrs provide full access to the many configurable parameters of the ethercat core. the indirectly accessibl e ethercat core csrs are accessed at address 0h through 0fffh and are detailed in section 12.14, "ethercat core csr register s (indirectly addressable)," on page 223 . figure 12-9: management access timing table 12-6: management access timing values symbol description min max units notes t clkp mii_mdc period 400 - ns t clkh mii_mdc high time 180 (90%) - ns t clkl mii_mdc low time 180 (90%) - ns t val mii_mdio output valid from rising edge of mii_mdc - 250 ns t ohold mii_mdio output hold from rising edge of mii_mdc 150 - ns t su mii_mdio input setup time to rising edge of mii_mdc 70 - ns t ihold mii_mdio input hold time after rising edge of mii_mdc 0-n s mii_mdc mii_mdio t clkh t clkl t clkp t ohold mii_mdio t su t ihold (data-out) (data-in) t ohold t val downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 209 lan9252 the ethercat core process data ram can be accessed indirectly via the ethercat csr interface data register (ecat_csr_data) and ethercat csr interface command register (ecat_csr_cmd) , starting at 1000h. the eth- ercat core process data ram can also be accessed more efficiently using the ethercat process ram read data fifo (ecat_pram_rd_data) and ethercat process ram write data fifo (ecat_pram_wr_data) . this method provides for multiple dwords to be transferre d via a fifo mechanism using a single command and fewer status reads. 12.11.1 ethercat csr reads to perform a read of an individual ethercat core register, the read cycle must be initiated by perfor ming a single write to the ethercat csr interface comma nd register (ecat_csr_cmd) with the csr busy (csr_busy) bit set, the csr address (csr_addr) field set to the desired register address, the read/write (r_nw) bit set and the csr size (csr_size) field set to the desired size. valid data is available for reading when the csr busy (csr_busy) bit is cleared, indicating that the data can be read from the ethercat csr interface data register (ecat_csr_data) . valid data is always aligned into the lowest bits of the ethercat csr interface data register (ecat_csr_data) . figure 12-10 illustrates the process required to perform a ethercat core csr read. minimum wait periods are required where noted. the minimum wait periods as specified in table 5-2, read after write timing rules, on page 35 are required where noted. note: all bytes of the ethercat csr interface data register (ecat_csr_data) are updated regardless of the value of csr size (csr_size) . figure 12-10: ethercat cs r read access flow diagram idle write command register read command register read data register csr_ busy = 0 csr read csr_ busy = 1 min wait period downloaded from: http:///
lan9252 ds00001909a-page 210 ? 2015 microchip technology inc. 12.11.2 ethercat csr writes to perform a write to an individual ethercat core register, the desired data must first be written into the ethercat csr interface data register (ecat_csr_data) . valid data is always aligned into the lowest bits of the ethercat csr inter- face data register (ecat_csr_data) . the write cycle is initiated by pe rforming a single write to the ethercat csr interface command register (ecat_cs- r_cmd) with the csr busy (csr_busy) bit set, the csr address (csr_addr) field set to the desired register address, the read/write (r_nw) bit cleared and the csr size (csr_size) field set to the desired size. the completion of the write cycle is indica ted by the cl earing of the csr busy (csr_busy) bit. figure 12-11 illustrates the process required to perform a ethercat core csr write. minimum wait periods are required where noted. minimum wait periods are required where noted. the minimum wait periods as specified in ta b l e 5 - 2 , read after write timing rules, on page 35 are required where noted. 12.11.3 ethercat process ram reads process data is transferred from the ethercat core through a 16 deep 32-bit wide fifo. the fifo has the base address of 00h, however, it is also accessible at seven addi tional contiguous memory lo cations. the host may access the fifo at any of these alias port locations, as they all function identically and contain the same data. this alias port addressing is implemented to allow hosts to burst through sequential addresses. for hbi access, the process ram read data fifo may also be accessed using fifo direct selection mode. in this mode, the address input is ignored and all read accesses are directed to the process ram read data fifo. see sec- tion 9.4.3.1, "fifo direct select access," on page 68 . figure 12-11: ethercat csr write access flow diagram idle write data register write command register read command register csr_ busy = 0 csr write csr_ busy = 1 min wait period downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 211 lan9252 to perform a read of the ethercat process ram, th e read cycle is initiated by first writing the ethercat process ram read address and length register (ecat_pram_rd_addr_len) with the starting byte address and length (in bytes) of the desired transfer followed by a write to the ethercat process ram read command register (ecat_pram_rd_cmd) with the pram read busy (pram_read_busy) bit set. valid data, as indicated by the pram read data available (pram_read_avail) bit in the ethercat process ram read command register (ecat_pram_rd_cmd) is read from the fifo through the ethercat process ram read data fifo (ecat_pram_rd_data) . the pram read data available count (pram_read_avail_cnt) field indi- cates how many reads can be performed without needing to check the status again. following the final read of the eth- ercat process ram read data fifo (ecat_pram_rd_data) , the pram read busy (pram_read_busy) self- clears. as the data is transferred from t he ethercat core into the fifo the pram read length (pram_read_len) and pram read address (pram_read_addr) are updated to show the progress. based on the starting address, the valid bytes in the first fifo read are as follows: based on the starting address and length, the valid bytes in the last fifo read are as follows: note: the starting byte address and length must be programm ed with valid values such that all transfers are within the bounds of the process ram address range of 1000h to 1fffh. note: the final read of the ethercat process ram read data fifo (ecat_pram_rd_data) implies that all four bytes have been read, even if not all bytes are required. table 12-7: ethercat process ram valid first read bytes starting address[1:0] 00b bytes 3, 2, 1 and 0 01b bytes 3, 2 and 1 10b bytes 3 and 2 11b byte 3 table 12-8: ethercat process ram valid last read bytes starting length[1:0] starting address[1:0] 01b (e.g. 5, 9, etc.) 10b (e.g. 6, 10, etc.) 1 1b (e.g. 7, 11, etc.) 00b (e.g. 8, 12, etc.) 00b byte 0 bytes 1 and 0 bytes 2, 1 and 0 bytes 3, 2, 1 and 0 01b bytes 1 and 0 bytes 2, 1 and 0 bytes 3, 2, 1 and 0 byte 0 10b bytes 2, 1 and 0 bytes 3, 2, 1 and 0 byte 0 bytes 1 and 0 11b bytes 3, 2, 1 and 0 byte 0 bytes 1 and 0 bytes 2, 1 and 0 downloaded from: http:///
lan9252 ds00001909a-page 212 ? 2015 microchip technology inc. if the initial length is 4 bytes of less and all bytes fit into one read, the valid bytes in the only fifo read are as follows: 12.11.3.1 aborting a read if necessary, a read command can be aborted by setting the pram read abort (pram_read_abort) bit in the eth- ercat process ram read command register (ecat_pram_rd_cmd) . 12.11.4 ethercat process ram writes process data is transferred to the ethercat core through a 16 deep 32-bit wide fifo. t he fifo has the base address of 20h, however, it is also accessible at seven additional contiguous memory locations. the host may access the fifo at any of these alias port locations, as they all function id entically and contain the same data. this alias port addressing is implemented to allow hosts to burst through sequential addresses. for hbi access, the process ram write data fifo may al so be accessed using fifo direct selection mode. in this mode, the address input is ignored and all write accesses are directed to the process ram write data fifo. see sec- tion 9.4.3.1, "fifo direct select access," on page 68 . to perform a write to the etherc at process ram, the write cycle is initiated by first writing the ethercat process ram write address and length register (ecat_pram_wr_addr_len) with the starting byte address and length (in bytes) of the desired transfe r followed by a write to the ethercat process ram write command register (ecat_pram_wr_cmd) with the pram write busy (pram_write_busy) bit set. . data is transferred into the ethercat core through a 16 deep 32-bit wide fifo. the host may write data to the fifo through the ethercat process ram write da ta fifo (ecat_pram_wr_data) when space is available as indicated by the pram write space available (pram_write_avail) bit in the ethercat process ram write command regis- ter (ecat_pram_wr_cmd) . the pram write space available count (pram_write_avail_cnt) field indicates how many writes can be performed withou t needing to check the status again. following the final write of the data into the ethercat core, the pram write busy (pram_write_busy) self-clears. as the data is transferred to the ethercat core fr om the fifo the pram write length (pram_write_len) and pram write address (pram_write_addr) are updated to show the progress. based on the starting address, the valid byte s in the first fifo write are as follows: table 12-9: ethercat process ram valid bytes one read starting length starting address[1:0] 4123 00b bytes 3, 2, 1 and 0 byte 0 byt es 1 and 0 bytes 2, 1 and 0 01b na byte 1 bytes 2 and 1 bytes 3, 2 and 1 10b na byte 2 bytes 3 and 2 na 1 1 b n ab y t e 3n a n a note: the starting byte address and length must be programm ed with valid values such that all transfers are within the bounds of the process ram address range of 1000h to 1fffh. note: the final write of the ethercat process ram write data fifo (ecat_pram_wr_data) implies that all four bytes have been written, even if not all bytes are required. downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 213 lan9252 based on the starting address and length, the vali d bytes in the last fifo write are as follows: if the initial length is 4 bytes of less and all bytes fit into one write, the valid bytes in the only fifo write are as follow s: 12.11.4.1 aborting a write if necessary, a write command can be aborted by setting the pram write abort (pram_write_abort) bit in the eth- ercat process ram write command register (ecat_pram_wr_cmd) . 12.12 ethercat reset after writing 0x52 (r), 0x45 (e) and 0x53 (s) into the esc reset ecat register with 3 consecutive fr ames or after writ- ing 0x52 (r), 0x45 (e) and 0x53 (s) into the esc reset pdi register with 3 consecutive wr ites, a device reset (and optional system reset) will occur, as defined in section 6.2.1.3, "ethercat system reset," on page 40 . table 12-10: ethercat process ram valid first write bytes starting address[1:0] 00b bytes 3, 2, 1 and 0 01b bytes 3, 2 and 1 10b bytes 3 and 2 11b byte 3 table 12-11: ethercat process ram valid last write bytes starting length[1:0] starting address[1:0] 01b (e.g. 5, 9, etc.) 10b (e.g. 6, 10, etc.) 1 1b (e.g. 7, 11, etc.) 00b (e.g. 8, 12, etc.) 00b byte 0 bytes 1 and 0 bytes 2, 1 and 0 bytes 3, 2, 1 and 0 01b bytes 1 and 0 bytes 2, 1 and 0 bytes 3, 2, 1 and 0 byte 0 10b bytes 2, 1 and 0 bytes 3, 2, 1 and 0 byte 0 bytes 1 and 0 11b bytes 3, 2, 1 and 0 byte 0 bytes 1 and 0 bytes 2, 1 and 0 table 12-12: ethercat process ram valid bytes one write starting length starting address[1:0] 4123 00b bytes 3, 2, 1 and 0 byte 0 byt es 1 and 0 bytes 2, 1 and 0 01b na byte 1 bytes 2 and 1 bytes 3, 2 and 1 10b na byte 2 bytes 3 and 2 na 1 1 b n ab y t e 3n a n a note: it is likely that the last frame of the sequence will not return to the master (depending on the topology), because the links to and from the slave which is reset will go down. downloaded from: http:///
lan9252 ds00001909a-page 214 ? 2015 microchip technology inc. 12.13 ethercat csr and process data ram access registers (directly addressable) this section details the directly addre ssable system csrs, outside of the ether cat core, which are related to the eth- ercat core. for information on how to access ethercat registers, refer to section 12.11, "ethercat csr and process data ram access," on page 208 . the ethercat core registers are detailed in section 12.14, "ethercat core csr registers (indirectly addressable)," on page 223 . table 12-13: ethercat process ram and csr access registers address register name (symbol) 000h-01ch ethercat process ram read data fifo (ecat_pram_rd_data) 020h-03ch ethercat process ram write data fifo (ecat_pram_wr_data) 300h ethercat csr interface data register (ecat_csr_data) 304h ethercat csr interface command register (ecat_csr_cmd) 308h ethercat process ram read address a nd length register (ecat_pram_rd_addr_len) 30ch ethercat process ram read command register (ecat_pram_rd_cmd) 310h ethercat process ram write address an d length register (ecat_pram_wr_addr_len) 314h ethercat process ram write co mmand register (ecat_pram_wr_cmd) downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 215 lan9252 12.13.1 ethercat process ram read data fifo (ecat_pram_rd_data) this read only register is used in conjunction with the ethercat process ram read command register (ecat_pram_rd_cmd) and the ethercat process ram read address and length register (ecat_pram_rd_addr_len) to perform read operations of the ethercat core process ram. data read from this register is only valid if the pram read data available (pram_read_avail) bit in the ethercat process ram read command register (ecat_pram_rd_cmd) is a 1. the host should not read this register unless there is valid data available. offset: 000h-01ch size: 32 bits bits description type default 31:0 ethercat process ram read data (pram_rd_data) this field contains the value read from the ethercat core process ram. note: some bytes maybe invalid based on the starting address and transfer length. ro - downloaded from: http:///
lan9252 ds00001909a-page 216 ? 2015 microchip technology inc. 12.13.2 ethercat process ram write data fifo (ecat_pram_wr_data) this write only register is used in conjunction with the ethercat process ram write command register (ecat_pram_wr_cmd) and the ethercat process ram write address and length register (ecat_pram_wr_addr_len) to perform write operations to the ethercat core process ram. the host should not write this register unless there is available space as indicated by the pram write space available (pram_write_avail) bit in the ethercat process ram write command register (ecat_pram_wr_cmd) . offset: 020h-03ch size: 32 bits bits description type default 31:0 ethercat process ram write data (pram_wr_data) this field contains the value writte n to the ethercat core process ram. note: some bytes maybe invalid based on the starting address and transfer length. wo - downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 217 lan9252 12.13.3 ethercat csr interface data register (ecat_csr_data) this read/write regist er is used in conjunction with the ethercat csr interface command register (ecat_csr_cmd) to perform read and write operations with the ethercat core csrs. offset: 300h size: 32 bits bits description type default 31:0 ethercat csr data (csr_data) this field contains the value read from or written to the ethercat core csr. the ethercat core csr is selected via the csr address (csr_addr) bits of the ethercat csr interface comm and register (ecat_csr_cmd) . valid data is always written to or read fr om the lower bits of this field. the h/ w handles any required byte alignment. upon a read, the value returned depends on the read/write (r_nw) bit in the ethercat csr interface command register (ecat_csr_cmd) . if read/write (r_nw) is set, the data is from the ethercat core. if read/write (r_nw) is cleared, the data is the value that was last written into this register. r/w 00000000h downloaded from: http:///
lan9252 ds00001909a-page 218 ? 2015 microchip technology inc. 12.13.4 ethercat csr interface command register (ecat_csr_cmd) this read/write register is used in conjunction with the ethercat csr interface data register (ecat_csr_data) to perform read and write operations with the ethercat core csrs. note 4: word and dword accesses must be aligned on the proper address boundary according to the following table. offset: 304h size: 32 bits bits description type default 31 csr busy (csr_busy) when a 1 is written to this bit, the r ead or write operation (as determined by the r_nw bit) is performed to the specified ethercat core csr in csr address (csr_addr) . this bit will remain set until the operat ion is complete, at which time the bit will self-clear. in the case of a read, t he clearing of this bit indicates to the host that valid data can be read from the ethercat csr interface data reg- ister (ecat_csr_data) . writing a 0 to this bit has no affect. the host should not modify the ethercat_csr_cmd and ether- cat_csr_data registers unless this bit is a 0. r/w sc 0b 30 read/write (r_nw) this bit determines whether a read or write operation is performed by the host to the specified ethercat core csr. 0: write 1: read r/w 0b 29:19 reserved ro - 18:16 csr size (csr_size) this field specifies the size of the ethercat core csr in bytes. valid values are 1, 2 and 4. the host should not use invalid values. note 4 . r/w 0h 15:0 csr address (csr_addr) this field selects the ethercat core csr that will be accessed with a read or write operation. this is a byte addr ess which is the format used to specify the offsets of the ethercat core csrs. note 4 . r/w 00h table 12-14: ethercat csr address vs. size csr_size[2:0] csr_addr[1:0] 1 00b, 01b, 10b, 11b 2 00b, 10b 40 0 b downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 219 lan9252 12.13.5 ethercat process ram read address and length register (ecat_pram_rd_addr_len) this read/write register is used in conjunction with the ethercat process ram read data fifo (ecat_pram_rd_- data) and the ethercat process ram read command register (ecat_pram_rd_cmd) to perform read operations from the ethercat core process ram. offset: 308h size: 32 bits note: the starting byte address and length must be programm ed with valid values such that all transfers are within the bounds of the process ram address range of 1000h to 1fffh. bits description type default 31:16 pram read length (pram_read_len) this field indicates the number of bytes to be read from the ethercat core process ram. it is decremented as data is read from the ethercat core and placed into the fifo. the host should not modify this field unless the pram read busy (pram_read_busy) bit is a low. r/w 0000h 15:0 pram read address (pram_read_addr) this field indicates the ethercat core byte address to be read. it is incre- mented as data is read from the et hercat core and placed into the fifo. note: the process ram starts at address 1000h. the host should not modify this field unless the pram read busy (pram_read_busy) bit is a 0. r/w 0000h downloaded from: http:///
lan9252 ds00001909a-page 220 ? 2015 microchip technology inc. 12.13.6 ethercat process ram read co mmand register (e cat_pram_rd_cmd) this read/write register is used in conjunction with the ethercat process ram read data fifo (ecat_pram_rd_- data) and the ethercat process ram read address and length register (ecat_pram_rd_addr_len) to per- form read operations from th e ethercat core process ram. offset: 30ch size: 32 bits bits description type default 31 pram read busy (pram_read_busy) when a 1 is written to this bit, the r ead operation is started beginning at the ethercat core process ram location specified in pram read address (pram_read_addr) for the length specified in pram read length (pram_read_len) . this bit will remain set until the entire read operation is complete, at which time the bit will self-clear. writing a 0 to this bit has no affect. r/w sc 0b 30 pram read abort (pram_read_abort) writing a 1 to this bit will cause the re ad operation in process to be canceled. the pram read busy (pram_read_busy) will be cleared and the read data fifo, along with the status bits, will be reset. this bit will self-clear. writing a 0 to this bit has no affect. r/w sc 0b 29:13 reserved ro - 12:8 pram read data available count (pram_read_avail_cnt) this field indicates the number of times that the ethercat process ram read data fifo (ecat_pram_rd_data) can be read without further need to check the status. this field increments as data is read from the ethercat core and placed into the fifo. this field is decremented when the a entire dword of data is read from the ethercat process ram read data fifo (ecat_pram_rd_- data) . ro 00000b 7:1 reserved ro - 0 pram read data avai lable (pram_read_avail) this field indicates that the ethercat process ram read data fifo (ecat_pram_rd_data) has valid data to be read. ro 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 221 lan9252 12.13.7 ethercat process ram writ e address and length register (ecat_pram_wr_addr_len) this read/write register is used in conjunction with the ethercat process ram write data fifo (ecat_pram_wr_- data) and the ethercat process ram write comm and register (ecat_pram_wr_cmd) to perform write opera- tions to the ethercat core process ram. offset: 310h size: 32 bits note: the starting byte address and length must be programm ed with valid values such that all transfers are within the bounds of the process ram address range of 1000h to 1fffh. bits description type default 31:16 pram write length (pram_write_len) this field indicates the number of byte s to be written to the ethercat core process ram. it is decremented as data is written to the ethercat core from the fifo. the host should not modify this field unless the pram write busy (pram_write_busy) bit is a low. r/w 0000h 15:0 pram write address (pram_write_addr) this field indicates the ethercat core byte address to be written. it is incre- mented as data is written to the ethercat core from the fifo. note: the process ram starts at address 1000h. the host should not modify this field unless the pram write busy (pram_write_busy) bit is a 0. r/w 0000h downloaded from: http:///
lan9252 ds00001909a-page 222 ? 2015 microchip technology inc. 12.13.8 ethercat process ram write co mmand register (e cat_pram_wr_cmd) this read/write register is used in conjunction with the ethercat process ram write data fifo (ecat_pram_wr_- data) and the ethercat process ram write address and length register (ecat_pram_wr_addr_len) to per- form write operations to the ethercat core process ram. offset: 314h size: 32 bits bits description type default 31 pram write busy (pram_write_busy) when a 1 is written to this bit, the wr ite operation is started beginning at the ethercat core process ram location specified in pram write address (pram_write_addr) for the length specified in pram write length (pram_write_len) . this bit will remain set until the entire write operation is complete, at which time the bit will self-clear. writing a 0 to this bit has no affect. r/w sc 0b 30 pram write abort (pram_write_abort) writing a 1 to this bit will cause the write operation in process to be canceled. the pram write busy (pram_write_busy) will be cleared and the write data fifo, along with the status bits, will be reset. this bit will self-clear. writing a 0 to this bit has no affect. r/w sc 0b 29:13 reserved ro - 12:8 pram write space available count (pram_write_avail_cnt) this field indicates the number of times that the ethercat process ram write data fifo (ecat_pram_wr_data) can be written without further need to check the status. this field is decremented when the a entire dword of data is written into the ethercat process ram write data fifo (ecat_pram_wr_data) . this field increments as data is read from the fifo and placed into the ether- cat core. ro 10000b 7:1 reserved ro - 0 pram write space available (pram_write_avail) this field indicates that the ethercat process ram write data fifo (ecat_pram_wr_data) has available space for data to be written. ro 1b downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 223 lan9252 12.14 ethercat core csr registers (indirectly addressable) this section details the indirectly addressable ethercat core csrs, which are accessed via the directly addressable ethercat csr interface data register (ecat_csr_data) and ethercat csr interface command register (ecat_csr_cmd) . for information on how to access ethercat registers, refer to section 12.11, "ethercat csr and process data ram access," on page 208 . the directly addressable ethercat registers are detailed in section 12.13, "ethercat csr and process data ram access re gisters (directly addressable)," on page 214 . note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. the read/write behavior of specific ethercat core register bits may differ depending on how the register is accessed. each ethercat core r egister includes ecat type and pdi type columns, which provide the bit/field type for register accesses via an etherca t master node or process data interface (spi / host bus), respectively. table 12-15: ethercat core csr registers address register name (symbol) esc information 0000h type register 0001h revision register 0002h-0003h build register 0004h fmmus supported register 0005h syncmanagers supported register 0006h ram size register 0007h port descriptor register 0008h-0009h esc features supported register station address 0010h-0011h configured station register 0012h-0013h configured station alias register write protection 0020h write register enable register 0021h write register protection register 0030h esc write register enable register 0031h esc write register protection register data link layer 0040h esc reset ecat register 0041h esc reset pdi register 0100h-0103h esc dl control register 0108h-0109h physical read/write offset register 0110h-0111h esc dl status register application layer 0120h-0121h al control register 0130h-0131h al status register 0134h-0135h al status code register 0138h run led override register 0139h reserved pdi (process data interface) 0140h pdi control register downloaded from: http:///
lan9252 ds00001909a-page 224 ? 2015 microchip technology inc. 0141h esc configuration register 0142h-0143h asic configuration register 0144h-0145h reserved register 0150h pdi configuration register 0151h sync/latch pdi configuration register 0152h-0153h extended pdi configuration register interrupts 0200h-0201h ecat event mask register 0204h-0207h al event mask register 0210h-0211h ecat event request register 0220h-0223h al event request register error counters 0300h-0307h rx error counter registers 0308h-030bh forwarded rx error counter registers 030ch ecat processing unit error counter register 030dh pdi error counter register 030eh pdi error code register 0310h-0313h lost link counter registers watchdogs 0400h-0401h watchdog divider register 0410h-0411h watchdog time pdi register 0420h-0421h watchdog time process data register 0440h-0441h watchdog status process data register 0442h watchdog counter process data register 0443h watchdog counter pdi register eeprom interface 0500h eeprom configuration register 0501h eeprom pdi access state register 0502h-0503h eeprom control/status register 0504h-0507h eeprom address register 0508h-050bh eeprom data register mii management interface 0510h-0511h mii management control/status register 0512h phy address register 0513h phy register address register 0514h-0515h phy data register 0516h mii management ecat access state register 0517h mii management pdi access state register 0518h-051bh phy port status registers 0600h-062fh fmmu[2:0] registers (3x16 bytes) +0h-3h fmmux logical start address register +4h-5h fmmux length register +6h fmmux logical start bit register +7h fmmux logical stop bit register table 12-15: ethercat core csr registers address register name (symbol) downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 225 lan9252 +8h-9h fmmux physical start address register +ah fmmux physical start bit register +bh fmmux type register +ch fmmux activate register +dh-fh fmmux reserved register 0630h-06ffh reserved 0800h-081fh syncmanager[3:0] registers (4x8 bytes) +0h-1h syncmanager x physical start address register +2h-3h syncmanager x length register +4h syncmanager x control register +5h syncmanager x status register +6h syncmanager x activate register +7h syncmanager x pdi control register 0820h-087fh reserved 0900h-09ffh distributed clocks (dc) distributed clocks - receive times 0900h-0903h receive time port 0 register 0904h-0907h receive time port 1 register 0908h-090bh receive time port 2 register 090ch-090fh reserved distributed clocks - time loop control unit 0910h-0917h system time register 0918h-091fh receive time ecat processing unit register 0920h-0927h system time offset register 0928h-092bh system time delay register 092ch-092fh system time difference register 0930h-0931h speed counter start register 0932h-0933h speed counter diff register 0934h system time difference filter depth register 0935h speed counter filter depth register distributed clocks - cyclic unit control 0980h cyclic unit control register distributed clocks - sync out unit 0981h activation register 0982h-0983h pulse length of syncsignals register 0984h activation status register 098eh sync0 status register 098fh sync1 status register 0990h-0997h start time cyclic operation register 0998h-099fh next sync1 pulse register 09a0h-09a3h sync0 cycle time register 09a4h-09a7h sync1 cycle time register distributed clocks - latch in unit 09a8h latch0 control register table 12-15: ethercat core csr registers address register name (symbol) downloaded from: http:///
lan9252 ds00001909a-page 226 ? 2015 microchip technology inc. 09a9h latch1 control register 09aeh latch0 status register 09afh latch1 status register 09b0h-09b7h latch0 time positive edge register 09b8h-09bfh latch0 time negative edge register 09c0h-09c7h latch1 time positive edge register 09c8h-09cfh latch1 time negative edge register distributed clocks - syncmanager event times 09f0h-09f3h ethercat buffer change event time register 09f8h-09fbh pdi buffer start time event register 09fch-09ffh pdi buffer change event time register esc specific 0e00h-0e07h product id register 0e08h-0e0fh vendor id register digital input/output 0f00h-0f01h digital i/o output data register 0f10h-0f11h general purpose output register 0f18h-0f19h general purpose input register user ram 0f80h-0fffh user ram process data ram 1000h-1001h digital i/o input data register 1000h-1fffh process data ram table 12-15: ethercat core csr registers address register name (symbol) downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 227 lan9252 12.14.1 type register 12.14.2 revision register 12.14.3 build register offset: 0000h size: 8 bits bits description ecat type pdi type default 7:0 ethercat controller type c0h = microchip. ro ro c0h offset: 0001h size: 8 bits bits description ecat type pdi type default 7:0 ethercat controller revision ro ro 02h offset: 0002h-0003h size: 16 bits bits description ecat type pdi type default 15:0 ethercat controller build [7:4] = minor version [3:0] = maintenance version ro ro 0000h note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. downloaded from: http:///
lan9252 ds00001909a-page 228 ? 2015 microchip technology inc. 12.14.4 fmmus supported register 12.14.5 syncmanagers supported register 12.14.6 ram size register offset: 0004h size: 8 bits bits description ecat type pdi type default 7:0 supported fmmus this field details the number of supported fmmu channels (or entities) of the ethercat slave c ontroller. the device provides 3. ro ro 03h offset: 0005h size: 8 bits bits description ecat type pdi type default 7:0 supported syncmanagers this field details the number of supported syncmanager chan- nels (or entities) of the etherca t slave controller. the device provides 4. ro ro 04h offset: 0006h size: 8 bits bits description ecat type pdi type default 7:0 process data ram size this field details the process data ram size included in the eth- ercat slave controller. the device provides 4kb. ro ro 04h downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 229 lan9252 12.14.7 port descriptor register offset: 0007h size: 8 bits bits description ecat type pdi type default 7:6 port 3 configuration this field details the port 3 configuration. 00: not implemented 01: not configured 10: ebus 11: mii/rmii ro ro 00b 5:4 port 2 configuration this field details the port 2 configuration. 00: not implemented 01: not configured 10: ebus 11: mii/rmii ro ro 11b (3-port operation) 01b (2-port operation) see section 14.0 chip mode configuration 3:2 port 1 configuration this field details the port 1 configuration. 00: not implemented 01: not configured 10: ebus 11: mii/rmii ro ro 11b 1:0 port 0 configuration this field details the port 0 configuration. 00: not implemented 01: not configured 10: ebus 11: mii/rmii ro ro 11b downloaded from: http:///
lan9252 ds00001909a-page 230 ? 2015 microchip technology inc. 12.14.8 esc features supported register offset: 0008h-0009h size: 16 bits bits description ecat type pdi type default 15:12 reserved ro ro 0h 11 fixed fmmu/syncmanager configuration 0: variable configuration 1: fixed configuration ro ro 0b 10 ethercat read/write command support 0: supported 1: not supported ro ro 0b 9 ethercat lrw command support 0: supported 1: not supported ro ro 0b 8 enhanced dc sync activation 0: not available 1: available note: this feature refers to the activation register and acti- vation status register ro ro 1b 7 separate handling of fcs errors 0: not supported 1: supported, frame with wrong fcs and additional nibble will be counted separately in forwarded rx counter ro ro 1b 6 enhanced link detection mii 0: not available 1: available ro ro 1b 5 enhanced link detection ebus 0: not available 1: available ro ro 0b 4 low jitter ebus 0: not available, standard jitter 1: available, jitter minimized ro ro 0b 3 distributed cl ocks (width) 0: 32-bit 1: 64-bit ro ro 1b 2 distributed clock 0: not available 1: available ro ro 1b 1 reserved ro ro 0b 0 fmmu operation 0: bit oriented 1: byte oriented ro ro 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 231 lan9252 12.14.9 configured station register 12.14.10 configured station alias register note 5: the default value of this field can be configured via eeprom. refer to section 12.8, "eeprom configu- rable registers," on page 201 for additional information. note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 12.14.11 write register enable register note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. offset: 0010h-0011h size: 16 bits bits description ecat type pdi type default 15:0 configured station address this field contains the address used for node addressing (fpxx commands) r/w ro 0000h note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. offset: 0012h-0013h size: 16 bits bits description ecat type pdi type default 15:0 configured station alias address this field contains the alias address used for node addressing (fpxx commands). the use of th is alias is activated by the sta- tion alias bit of the esc dl control register . note: eeprom value is only taken over at first eeprom load after lower-on reset. ro r/w 0000h note 5 offset: 0020h size: 8 bits downloaded from: http:///
lan9252 ds00001909a-page 232 ? 2015 microchip technology inc. bits description ecat type pdi type default 7:1 reserved write 0. ro ro 0000000b 0 write register enable if write protection is enabled, this register must be written in the same ethernet frame (value is a dont care) before other writes to this station are allowed. write pr otection is still active after this frame (if the write register protection register is not changed) r/w ro 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 233 lan9252 12.14.12 write register protection register 12.14.13 esc write register enable register offset: 0021h size: 8 bits bits description ecat type pdi type default 7:1 reserved write 0. ro ro 0000000b 0 write register protection 0: protection disabled 1: protection enabled note: registers 0000h-0f0fh are write protected, except for 0030h. r/w ro 0b offset: 0030h size: 8 bits bits description ecat type pdi type default 7:1 reserved write 0. ro ro 0000000b 0 esc write register enable if esc write protection is enabled, this register must be written in the same ethernet frame (value is a dont care) before other writes to this station are allowed. esc write protection is still active after this frame (if the esc write register protection reg- ister is not changed) r/w ro 0b downloaded from: http:///
lan9252 ds00001909a-page 234 ? 2015 microchip technology inc. 12.14.14 esc write register protection register 12.14.15 esc reset ecat register offset: 0031h size: 8 bits bits description ecat type pdi type default 7:1 reserved write 0. ro ro 0000000b 0 esc write register protection 0: protection disabled 1: protection enabled note: all areas are write protected, except for 0030h. r/w ro 0b offset: 0040h size: 8 bits bits description ecat type pdi type default write 7:0 esc reset ecat a reset is asserted after writing 52h (r), 45h (e), and 53h (s) in this register with 3 consecutive commands. r/w ro 00h read 7:2 reserved ro ro 000000b 1:0 reset procedure progress 01: after writing 52h 10: after writing 45h (if 52h previously written) 00: else r/w ro 00b downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 235 lan9252 12.14.16 esc reset pdi register offset: 0041h size: 8 bits bits description ecat type pdi type default write 7:0 esc reset pdi a reset is asserted after writing 52h (r), 45h (e), and 53h (s) in this register with 3 consecutive commands. ro r/w 00h read 7:2 reserved ro ro 000000b 1:0 reset procedure progress 01: after writing 52h 10: after writing 45h (if 52h previously written) 00: else ro r/w 00b downloaded from: http:///
lan9252 ds00001909a-page 236 ? 2015 microchip technology inc. 12.14.17 esc dl control register offset: 0100h-0103h size: 32 bits bits description ecat type pdi type default 31:25 reserved write 0. ro ro 0000000b 24 station alias 0: ignore station alias 1: alias can be used for all configured address command types (fprd, fpwr, etc.) r/w ro 0b 23:20 reserved write 0. ro ro 0000b 19 ebus low jitter 0: normal jitter 1: reduced jitter r/w ro 0b 18:16 rx fifo size/rx delay reduction (esc delays start of forwarding until fifo is at least half full) see note 6 . ebus mii 000: -50 ns -40 ns 001: -40 ns -40 ns 010: -30 ns -40 ns 011: -20 ns -40 ns 100: -10 ns no change 101: no change no change 110: no change no change 111: default default r/w ro 111b 15:14 reserved write 0. ro ro 00b 13:12 loop port 2 00: auto. 01: auto close. 10: open. 11: closed. r/w note 7 ro 00b 11:10 loop port 1 00: auto. 01: auto close. 10: open. 11: closed. r/w note 7 ro 00b 9:8 loop port 0 00: auto. 01: auto close. 10: open. 11: closed. r/w note 7 ro 00b 7:2 reserved write 0. ro ro 000000b downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 237 lan9252 note 6: the possibility of rx fifo size reduction depends on the clock source accuracy of the esc and of every connected ethercat/ethernet dev ice (master, slave, etc. ). rx fifo size of 111b is sufficient for 100ppm accuracy, rx fifo size 000b is possible with 25ppm accuracy (frame size of 1518/1522 byte). note 7: loop configuration changes are delayed until the end of a currently received or transmitted frame at the port. note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 12.14.18 physical read/write offset register note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 1 temporary use of register 0101h settings 0: permanent use 1: temporarily use for ~1 s, then revert to previous settings. r/w ro 0b 0 forwarding rule 0: ethercat frames are processed, non-ethercat frames are forwarded without processing 1: ethercat frame are processed, non-ethercat frames are destroyed. the source mac address is changed for every frame (source_mac[1] is set to 1 - locally administered address) regardless of the forwarding rule. r/w ro 1b offset: 0108h-0109h size: 16 bits bits description ecat type pdi type default 15:0 physical read/write offset offset of r/w commands (fprw, aprw) between read address and write address. rd_adr - adr and wr_adr = adr + r/w-offset. r/w ro 0b bits description ecat type pdi type default downloaded from: http:///
lan9252 ds00001909a-page 238 ? 2015 microchip technology inc. 12.14.19 esc dl status register offset: 0110h-0111h size: 16 bits bits description ecat type pdi type default 15:14 reserved ro ro 00b 13 communication on port 2 0: no stable communication 1: communication established ro ro 0b 12 loop port 2 0: open. 1: closed. ro ro 0b 11 communication on port 1 0: no stable communication 1: communication established ro ro 0b 10 loop port 1 0: open. 1: closed. ro ro 0b 9 communication on port 0 0: no stable communication 1: communication established ro ro 0b 8 loop port 0 0: open. 1: closed. ro ro 0b 7 reserved ro ro 0b 6 physical link on port 2 0: no link 1: link detected ro ro 0b 5 physical link on port 1 0: no link 1: link detected ro ro 0b 4 physical link on port 0 0: no link 1: link detected ro ro 0b 3 reserved ro ro 0b 2 enhanced link detection 0: deactivated for all ports 1: activated for at least one port note: eeprom value is only taken over at first eeprom load after power-on reset. ro ro 0b (until first eeprom load, then eeprom adr 0000h bit 9 or 0000h[15:12]) 1 pdi watchdog status 0: watchdog expired 1: watchdog reloaded ro ro 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 239 lan9252 12.14.20 al control register note 8: this register behaves like a mailbox if device emulation is off ( device emulation bit of esc configuration register is 0). the pdi must read this register after ecat has written it. otherwise, ecat can not write again to this register. after rest, this register can be written by ecat. regarding mailbox functionality, both registers 0120h and 0121h are equivalent, e.g., reading 0121h is sufficient to make this register writable again. if device emulation is on, th is register can always be written and it contents are copied to the al status register . reading this register from pdi clears all event requests (register 0220h bit 0). note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 0 pdi operational/eeprom loaded correctly 0: eeprom not loaded, pdi not operational (no access to pro- cess data ram) 1: eeprom loaded correctly, pdi operational (access to pro- cess data ram) ro ro 0b note: reading this register from ecat clears the dl status event bit in the ecat event request register . for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. offset: 0120h-0121h size: 16 bits bits description ecat type pdi type default 15:5 reserved write as 0. r/w note 8 r/wc 000h 4 error ind ack0: no ack of error ind in al status register 1: ack of error ind in al status register r/w note 8 r/wc 0b 3:0 initiate state transition of device state machine 1h: request init state 2h: request pre-operational state 3h: request bootstrap state 4h: request safe-operational state 8h: request operational state r/w note 8 r/wc 1h bits description ecat type pdi type default downloaded from: http:///
lan9252 ds00001909a-page 240 ? 2015 microchip technology inc. 12.14.21 al status register note 9: this register is only writable if device emulation is off ( device emulation bit of esc configuration register is 0). otherwise, this register will reflect the al control register values. reading this register from ecat clears the al status event bit in the ecat event request register . note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 12.14.22 al status code register offset: 0130h-0131h size: 16 bits bits description ecat type pdi type default 15:5 reserved write as 0. ro r/w note 9 000h 4 error ind0: device is in state as requested or flag cleared by command 1: device has not entered reques ted state or changed state as a result of a local action ro r/w note 9 0b 3:0 actual state of the device state machine 1h: init state 2h: pre-operational state 3h: bootstrap state 4h: safe-operational state 8h: operational state ro r/w note 9 1h offset: 0134h-0135h size: 16 bits bits description ecat type pdi type default 15:0 al status code ro r/w 0000h note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 241 lan9252 12.14.23 run led override register offset: 0138h size: 8 bits bits description ecat type pdi type default 7:5 reserved write 0. r/w r/w 000b 4 run override 0: override disabled 1: override enabled r/w r/w 0b 3:0 run led code code fsm state 0h: off 1 - init 1h-ch: flash 1x-12x 4 - safeop 1x dh: blinking 2 - preop eh: flickering 3 - bootstrap fh: on 8 - op r/w r/w 0h note: changes to al status register with valid values will disable run override (bit 4 = 0). the value read in this register always reflects the current led output. downloaded from: http:///
lan9252 ds00001909a-page 242 ? 2015 microchip technology inc. 12.14.24 pdi control register note 10: the default value of this field can be configured via eeprom. refer to section 12.8, "eeprom configu- rable registers," on page 201 for additional information. offset: 0140h size: 8 bits bits description ecat type pdi type default 7:0 process data interface 04h: digital i/o 80h: spi 88h: hbi multiplexed 1 phase 8-bit 89h: hbi multiplexed 1 phase 16-bit 8ah: hbi multiplexed 2 phase 8-bit 8bh: hbi multiplexed 2 phase 16-bit 8ch: hbi indexed 8-bit 8dh: hbi indexed 16-bit others: reserved ro ro 00h note 10 downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 243 lan9252 12.14.25 esc configuration register note 11: the default value of this field can be configured via eeprom. refer to section 12.8, "eeprom configu- rable registers," on page 201 for additional information. note: this register is initialized from the contents of the eeprom. the eeprom settings for enhanced link detection (bits 6,5,4,1) are only taken at the first eeprom loadi ng after power-on reset. changing the eeprom and manually reloading it will not affect the enhanced link detection enable status, even if the eeprom could not be read initially. offset: 0141h size: 8 bits bits description ecat type pdi type default 7 reserved ro ro 0b 6 enhanced link port 2 0: disabled (if bit 1 = 0) 1: enabled ro ro 0b note 11 5 enhanced link port 1 0: disabled (if bit 1 = 0) 1: enabled ro ro 0b note 11 4 enhanced link port 0 0: disabled (if bit 1 = 0) 1: enabled ro ro 0b note 11 3 distributed clocks latch in unit 0: disabled (power saving) 1: enabled note: this bit has no affect. ro ro 0b 2 distributed clocks sync out unit 0: disabled (power saving) 1: enabled note: this bit has no affect. ro ro 0b 1 enhanced link detection all ports 0: disabled (if bits [7:4] = 0) 1: enabled all ports ro ro 0b note 11 0 device emulation (control of al status register ) 0: al status register must be set by pdi 1: al status register set to value written to al control register note: the value programmed should be 1 for digital i/o mode and 0 for applications with a host controller. ro ro 0b note 11 downloaded from: http:///
lan9252 ds00001909a-page 244 ? 2015 microchip technology inc. 12.14.26 asic configuration register note 12: the default value of this field can be configured via eeprom. refer to section 12.8, "eeprom configu- rable registers," on page 201 for additional information. note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 12.14.27 reserved register note 13: the default value of this field can be configured via eeprom. refer to section 12.8, "eeprom configu- rable registers," on page 201 for additional information. note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. offset: 0142h-0143h size: 16 bits bits description ecat type pdi type default 15 mi link detection (link configuration, lin k detection, registers phy port status registers ) 0: not available 1: mi link detection active ro ro 0b note 12 14:6 reserved ro ro 0000000b note 12 7 mi write gigabit register 9 enable enables writes to phy register 9 for phys which use this regis- ter per ieee 802.30: mi writes to gigabit register 9 disabled 1: mi writes to gigabit register 9 enabled ro ro 0b note 12 6:0 reserved ro ro 0000000b note 12 offset: 0144h-0145h size: 16 bits bits description ecat type pdi type default 15:0 reserved ro ro 0000h note 13 downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 245 lan9252 12.14.28 pdi configuration register the bit definitions of this register are dependent on the selected pdi mode ( process data interface field in the pdi con- trol register ): digital i/o mode or hbi modes. pdi configuration register: digital i/o mode note 14: the default value of this field can be configured via eeprom. refer to section 12.8, "eeprom configu- rable registers," on page 201 for additional information. offset: 0150h size: 8 bits bits description ecat type pdi type default 7:6 output data sample selection 00: end of frame 01: reserved 10: dc sync0 event 11: dc sync1 event note: if outvalid mode = 1, output data is updated at process data watchdog trigger event ( output data sample selection bit ignored) ro ro 00b note 14 5:4 input data sample selection 00: end of frame 01: rising edge of latch_in 10: dc sync0 event 11: dc sync1 event ro ro 00b note 14 3 watchdog behavior 0: outputs are reset immediately after watchdog expires 1: outputs are reset with next output event that follows watchdog expiration ro ro 0b note 14 2 unidirectional/bidirectional mode 0: unidirectional mode: input/output direction of pins configured individually 1: bidirectional mode: all i/o pins are bidirectional, direction con- figuration is ignored ro ro 0b note 14 1 outvalid mode 0: output event signaling 1: process data watchdog trigger (wd_trig) signaling on outvalid. output data is updated if watchdog is triggered. overrides output data sample selection bit. ro ro 0b note 14 0 outvalid polarity 0: active high 1: active low ro ro 0b note 14 downloaded from: http:///
lan9252 ds00001909a-page 246 ? 2015 microchip technology inc. pdi configuration register: hbi modes note 15: the default value of this field can be configured via eeprom. refer to section 12.8, "eeprom configu- rable registers," on page 201 for additional information. bits description ecat type pdi type default 7 hbi ale qual ification configures the hbi interface to qualify the alehi and alelo signals with the cs signal. 0: address input is latched with alehi and alelo 1: address input is latched with alehi and alelo only when cs is active. ro ro 0b note 15 6 hbi read/write mode configures the hbi interface for separate read and write signals or direction and enable signals. 0: read and write 1: direction and enable ro ro 0b note 15 5 hbi chip sel ect polarity configures the polarity of the hbi interface chip select signal. 0: active low 1: active high ro ro 0b note 15 4 hbi read, read/write polarity configures the polarity of the hbi interface read signal. 0: active low read 1: active high read configures the polarity of the hbi interface read/write signal. 0: read when 1, write when 0 (r/nw) 1: write when 1, read when 0 (w/nr) ro ro 0b note 15 3 hbi write, enable polarity configures the polarity of the hbi interface write signal. 0: active low write 1: active high write configures the polarity of the hbi interface read/write signal. 0: active low enable 1: active high enable ro ro 0b note 15 2 hbi ale polarity configures the polarity of the hbi interface alehi and alelo signals. 0: active low strobe (address saved on rising edge) 1: active high strobe (address saved on falling edge) ro ro 0b note 15 1:0 reserved ro ro 00b note 15 downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 247 lan9252 12.14.29 sync/latch pdi configuration register note 16: the default value of this field can be configured via eeprom. refer to section 12.8, "eeprom configu- rable registers," on page 201 for additional information. offset: 0151h size: 8 bits bits description ecat type pdi type default 7 sync1 map sync1 mapped to al event request register (0220h bit 3) 0: disabled 1: enabled ro ro 0b note 16 6 sync1/latch1 configuration 0: latch1 input 1: sync1 output ro ro 0b note 16 5:4 sync1 output driver/polarity 00: push-pull active low 01: open drain (active low) 10: push-pull active high 11: open source (active high) ro ro 00b note 16 3 sync0 map sync0 mapped to al event request register (0220h bit 2) 0: disabled 1: enabled ro ro 0b note 16 2 sync0/latch0 configuration 0: latch0 input 1: sync0 output ro ro 0b note 16 1:0 sync0 output driver/polarity 00: push-pull active low 01: open drain (active low) 10: push-pull active high 11: open source (active high) ro ro 00b note 16 downloaded from: http:///
lan9252 ds00001909a-page 248 ? 2015 microchip technology inc. 12.14.30 extended pdi configuration register the bit definitions of this register are dependent on the selected pdi mode ( process data interface field in the pdi con- trol register ): digital i/o mode or spi mode. extended pdi configuration register: digital i/o mode note 17: the default value of this field can be configured via eeprom. refer to section 12.8, "eeprom configu- rable registers," on page 201 for additional information. note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. offset: 0152h-0153h size: 16 bits bits description ecat type pdi type default 15:8 reserved ro ro 0000h 7 i/o[15:14] direction 0: input 1: output note: reserved in bidirectional mode (0b). ro ro 0b note 17 6 i/o[13:12] direction 0: input 1: output note: reserved in bidirectional mode (0b). ro ro 0b note 17 5 i/o[11:10] direction 0: input 1: output note: reserved in bidirectional mode (0b). ro ro 0b note 17 4 i/o[9:8] direction 0: input 1: output note: reserved in bidirectional mode (0b). ro ro 0b note 17 3 i/o[7:6] direction 0: input 1: output note: reserved in bidirectional mode (0b). ro ro 0b note 17 2 i/o[5:4] direction 0: input 1: output note: reserved in bidirectional mode (0b). ro ro 0b note 17 1 i/o[3:2] direction 0: input 1: output note: reserved in bidirectional mode (0b). ro ro 0b note 17 0 i/o[1:0] direction 0: input 1: output note: reserved in bidirectional mode (0b). ro ro 0b note 17 downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 249 lan9252 pdi configuration register: spi mode bits description ecat type pdi type default 15 i/o[15:14] buffer type 0: push-pull 1: open drain ro ro 0b note 18 14 i/o[13:12] buffer type 0: push-pull 1: open drain ro ro 0b note 18 13 i/o[11:10] buffer type 0: push-pull 1: open drain ro ro 0b note 18 12 i/o[9:8] buffer type 0: push-pull 1: open drain ro ro 0b note 18 11 i/o[7:6] buffer type 0: push-pull 1: open drain ro ro 0b note 18 10 i/o[5:4] buffer type 0: push-pull 1: open drain ro ro 0b note 18 9 i/o[3:2] buffer type 0: push-pull 1: open drain ro ro 0b note 18 8 i/o[1:0] buffer type 0: push-pull 1: open drain ro ro 0b note 18 7 i/o[15:14] direction 0: input 1: output ro ro 0b note 18 6 i/o[13:12] direction 0: input 1: output ro ro 0b note 18 5 i/o[11:10] direction 0: input 1: output ro ro 0b note 18 4 i/o[9:8] direction 0: input 1: output ro ro 0b note 18 3 i/o[7:6] direction 0: input 1: output ro ro 0b note 18 2 i/o[5:4] direction 0: input 1: output ro ro 0b note 18 1 i/o[3:2] direction 0: input 1: output ro ro 0b note 18 downloaded from: http:///
lan9252 ds00001909a-page 250 ? 2015 microchip technology inc. note 18: the default value of this field can be configured via eeprom. refer to section 12.8, "eeprom configu- rable registers," on page 201 for additional information. note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 12.14.31 ecat event mask register note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 12.14.32 al event mask register note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 0 i/o[1:0] direction 0: input 1: output ro ro 0b note 18 offset: 0200h-0201h size: 16 bits bits description ecat type pdi type default 15:0 ecat event mask ecat event masking of the ecat event request register events for mapping into the ecat event fields of ethercat frames. 0: corresponding ecat event request register bit is not mapped 1: corresponding ecat event request register bit is mapped r/w ro 0000h offset: 0204h-0207h size: 32 bits bits description ecat type pdi type default 31:0 al event mask al event masking of the al event request register events for mapping to the pdi irq signal. 0: corresponding al event request register bit is not mapped 1: corresponding al event request register bit is mapped ro r/w 00ffff0fh bits description ecat type pdi type default downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 251 lan9252 12.14.33 ecat event request register note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. offset: 0210h-0211h size: 16 bits bits description ecat type pdi type default 15:8 reserved ro ro 00h 7 syncmanager status mirror this bit mirrors the value of the syncmanager channel 3 status. 0: no sync channel 3 event 1: sync channel 3 event pending ro ro 0b 6 syncmanager status mirror this bit mirrors the value of the syncmanager channel 2 status. 0: no sync channel 2 event 1: sync channel 2 event pending ro ro 0b 5 syncmanager status mirror this bit mirrors the value of the syncmanager channel 1 status. 0: no sync channel 1 event 1: sync channel 1 event pending ro ro 0b 4 syncmanager status mirror this bit mirrors the value of the syncmanager channel 0 status. 0: no sync channel 0 event 1: sync channel 0 event pending ro ro 0b 3 al status event 0: no change in al status 1: al status change note: this bit is cleared by reading the al status register from ecat. ro ro 0b 2 dl status event 0: no change in dl status 1: dl status change note: this bit is cleared by reading the esc dl status reg- ister from ecat. ro ro 0b 1 reserved ro ro 0b 0 dc latch event 0: no change on dc latch inputs 1: at least one change on dc latch inputs note: this bit is cleared by reading the dc latch event times from ecat for ecat controlled latch units, so that the latch0 status register / latch1 status register indicates no event. ro ro 0b downloaded from: http:///
lan9252 ds00001909a-page 252 ? 2015 microchip technology inc. 12.14.34 al event request register offset: 0220h-0223h size: 32 bits bits description ecat type pdi type default 31:12 reserved ro ro 000h 11 syncmanager 3 interrupts (syncmanager register offset 5h, bit 0 or 1) 0: no syncmanager 3 interrupt 1: syncmanager 3 interrupt pending ro ro 0b 10 syncmanager 2 interrupts (syncmanager register offset 5h, bit 0 or 1) 0: no syncmanager 2 interrupt 1: syncmanager 2 interrupt pending ro ro 0b 9 syncmanager 1 interrupts (syncmanager register offset 5h, bit 0 or 1) 0: no syncmanager 1 interrupt 1: syncmanager 1 interrupt ro ro 0b 8 syncmanager 0 interrupts (syncmanager register offset 5h, bit 0 or 1) 0: no syncmanager 0 interrupt 1: syncmanager 0 interrupt pending ro ro 0b 7 reserved ro ro 0b 6 watchdog process data 0: has not expired 1: has expired note: this bit is cleared by reading the watchdog status process data register . ro ro 0b 5 eeprom emulation0: no command pending 1: eeprom command pending note: this bit is cleared by acknowledging the command in eeprom control/status register from pdi. ro ro 0b 4 syncmanager x activation register changed ( syncmanager x activate register ) 0: no change in any syncmanager 1: at least one syncmanager changed note: this bit is cleared by reading the corresponding syn- cmanager x activate register from pdi. ro ro 0b 3 state of dc sync1 (if sync/latch pdi configuration register bit 7 = 1) note: bit is cleared by reading sync1 status 0x098f. ro ro 0b 2 state of dc sync0 (if sync/latch pdi configuration register bit 3 = 1) note: bit is cleared by reading sync0 status 0x098e. ro ro 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 253 lan9252 note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 1 dc latch event 0: no change on dc latch inputs 1: at least one change on dc latch inputs note: this bit is cleared by reading the dc latch event times from pdi for pdi controlled latch units, so that the latch0 status register / latch1 status register indicates no event. ro ro 0b 0 al control event 0: no al control register change 1: al control register has been written (al control event is only generated if pdi emulation is turned off ( esc configuration register bit 8 = 0). note: this bit is cleared by reading the al control register from pdi. ro ro 0b bits description ecat type pdi type default downloaded from: http:///
lan9252 ds00001909a-page 254 ? 2015 microchip technology inc. 12.14.35 rx error counter registers there are 4 16-bit rx error counter registers, each wit h unique address offsets as shown above. the variable x is used in the following bit descriptions to represent ports 0-3. note: this register is cleared if any one of the rx error counter registers is written. note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. note: port 3 is not used. offset: 0300h-0307h port 0: 0300h-0301h port 1: 0302h-0303h port 2: 0304h-0305h port 3: 0306h-0307h size: 16 bits bits description ecat type pdi type default 15:8 port x rx error counter counting is stopped when ffh is reached. this is coupled directly to rx err of the mii/ebus interfaces. r/wc ro 00h 7:0 port x invalid frame counter counting is stopped when ffh is reached. r/wc ro downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 255 lan9252 12.14.36 forwarded rx error counter registers there are 4 8-bit forwarded rx error counter registers, ea ch with unique address offsets as shown above. the variable x is used in the following bit descriptions to represent ports 0-3. note: this register is cleared if any one of the rx error counter registers is written. note: port 3 is not used. 12.14.37 ecat processing un it error counter register 12.14.38 pdi error counter register offset: 0308h-030bh port 0: 0308h port 1: 0309h port 2: 030ah port 3: 030bh size: 8 bits bits description ecat type pdi type default 7:0 port x forwarded rx error counter counting is stopped when ffh is reached. this is coupled directly to rx err of the mii/ebus interfaces. r/wc ro 00h offset: 030ch size: 8 bits bits description ecat type pdi type default 7:0 ecat processing unit error counter counting is stopped when ffh is reached. this field counts the errors of frames passing the proc essing unit (e.g., fcs error or datagram structure error). r/wc ro 00h offset: 030dh size: 8 bits bits description ecat type pdi type default 7:0 pdi error counter counting is stopped when ffh is reached. this field counts if a pdi access has an interface error. r/wc ro 00h downloaded from: http:///
lan9252 ds00001909a-page 256 ? 2015 microchip technology inc. 12.14.39 pdi error code register the bit definitions of this register are dependent on the selected pdi mode ( process data interface field in the pdi con- trol register ): spi mode or hbi modes. note: this register is cleared when the pdi error counter register is written. pdi error codes: spi mode pdi error codes: hbi modes offset: 030eh size: 8 bits bits description ecat type pdi type default 7:0 reserved ro ro 00h bits description ecat type pdi type default 7:0 reserved ro ro 00h downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 257 lan9252 12.14.40 lost link counter registers there are 4 8-bit lost link counter re gisters, each with unique address offs ets as shown above. the variable x is used in the following bit descriptions to represent ports 0-3. note: this register is cleared if any one of the lost link counter registers is written. note: port 3 is not used. 12.14.41 watchdog divider register note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. offset: 0310h-0313h port 0: 0310h port 1: 0311h port 2: 0312h port 3: 0313h size: 8 bits bits description ecat type pdi type default 7:0 port x lost link counter counting is stopped when ffh is reached. this counter only counts if port loop is auto or auto-close. note: only lost links at open ports are counted. r/wc ro 00h offset: 0400h-0401h size: 16 bits bits description ecat type pdi type default 15:0 watchdog divider number of 25mhz ticks (minus 2) that represents the basic watchdog increment. (default value is 100 us = 2498) r/w ro 09c2h downloaded from: http:///
lan9252 ds00001909a-page 258 ? 2015 microchip technology inc. 12.14.42 watchdog time pdi register note: the watchdog is disabled if watchdog time pdi is set to 0000h. watchdog is restarted with every pdi access. note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 12.14.43 watchdog time process data register note: there is one watchdog for all syncmanagers. the watchdog is disabled if watchdog time pdi is set to 0000h. the watchdog is restarted with ever y write access to the syncmanagers with the watchdog trigger enable bit set. note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. offset: 0410h-0411h size: 16 bits bits description ecat type pdi type default 15:0 watchdog time pdi number of basic watchdog increments. (default value with watchdog divider of 100 us results in 100 ms watchdog.) r/w ro 03e8h offset: 0420h-0421h size: 16 bits bits description ecat type pdi type default 15:0 watchdog time process data number of basic watchdog increments. (default value with watchdog divider of 100 us results in 100 ms watchdog.) r/w ro 03e8h downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 259 lan9252 12.14.44 watchdog status process data register note: reading this register clears the watchdog process data bit of the al event request register . note: the watchdog status for the pdi can be read in the pdi watchdog status bit of the esc dl status register . note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 12.14.45 watchdog counter process data register 12.14.46 watchdog counter pdi register offset: 0440h-0441h size: 16 bits bits description ecat type pdi type default 15:1 reserved ro ro 0000h 0 watchdog status of process data (triggered by syncmanagers) 0: watchdog process data expired 1: watchdog process data is active or disabled ro ro 0b offset: 0442h size: 8 bits bits description ecat type pdi type default 7:0 watchdog counter process data counting is stopped when ffh is reached. counts if process data watchdog expires. this field is cleared if one of the watch- dog counters ( 0442h - 0443h ) is written. r/wc ro 00h offset: 0443h size: 8 bits bits description ecat type pdi type default 7:0 watchdog pdi counter counting is stopped when ffh is reached. counts if pdi watch- dog expires. this field is cleared if one of the watchdog counters ( 0442h - 0443h ) is written. r/wc ro 00h downloaded from: http:///
lan9252 ds00001909a-page 260 ? 2015 microchip technology inc. 12.14.47 eeprom conf iguration register note: ethercat controls the sii eeprom interface if the pdi eeprom control bit of the eeprom configuration register is 0 and the access to eeprom bit of the eeprom pdi access state register is 0. otherwise, pdi controls the eeprom interface. offset: 0500h size: 8 bits bits description ecat type pdi type default 7:2 reserved write 0. ro ro 000000b 1 force ecat access 0: do not change 1: reset r/w ro 0b 0 pdi eeprom control 0: no 1: yes (pdi has eeprom control) r/w ro 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 261 lan9252 12.14.48 eeprom pdi access state register note 19: write access only possible if the pdi eeprom control bit of the eeprom configuration register is 1 and force ecat access bit is 0. note: ethercat controls the si i eeprom interface if the pdi eeprom control bit of the eeprom configuration register is 0 and the access to eeprom bit of the eeprom pdi access state register is 0. otherwise, pdi controls the eeprom interface. 12.14.49 eeprom control/status register offset: 0501h size: 8 bits bits description ecat type pdi type default 7:1 reserved write 0. ro ro 0000000b 0 access to eeprom 0: do not change 1: reset ro r/w note 19 0b offset: 0502h-0503h size: 16 bits bits description ecat type pdi type default 15 busy 0: eeprom interface is idle 1: eeprom interface is busy ro ro 0b 14 error write enable 0: no error 1: write command without write enable (see note 20 ) ro ro 0b 13 error acknowledge/command 0: no error 1: missing eeprom acknowl edge or invalid command (see note 20 ) note: eeprom emulation only: pdi writes 1 if a temporary failure has occurred. ro r/[w] note 21 0b 12 eeprom loading status 0: eeprom loaded, device information okay 1: eeprom not loaded, device information not available (eeprom loading in-progress or finished with a failure) ro ro 0b 11 checksum error in esc configuration area 0: checksum okay 1: checksum error ro r/[w] note 21 0b downloaded from: http:///
lan9252 ds00001909a-page 262 ? 2015 microchip technology inc. note 20: error bits are cleared by writing 000 (or any valid command) to command register bits. note 21: write access is possible if eeprom interface is busy ( busy bit = 1). pdi acknowledges pending commands by writing a 1 into the corresponding command register bi ts 10:8. errors can be indicated by writing a 1 into the error bits (11 and 13). acknowledging clears bit 5 of the al event request register . note 22: the command register bits are self clearing after the command is executed (eeprom busy ends). writing 000 to the command register bits will also clear the error bits 14:13. the command register bits are ignored if the error acknowledge/command is pending. note 23: the default of this bit is dependent on the eeprom_size_strap . note 24: the ecat write enable bit is self clearing at t he sof of the next frame. note: ethercat controls the sii eeprom interface if the pdi eeprom control bit of the eeprom configuration register is 0 and the access to eeprom bit of the eeprom pdi access state register is 0. otherwise, pdi controls the eeprom interface. note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 10:8 command register write: initiate command read: currently executed command 000: no command/eeprom idle (clear error bits) 001: read 010: write 100: reload others: reserved / invalid commands (no not issue) (see note 22 ) r/w r/[w] note 21 000b 7 selected eeprom algorithm0: 1 address byte (1kbit - 16kbit eeproms) 1: 2 address bytes (32kbit - 4mbit eeproms) ro ro note 23 6 supported number of eeprom bytes 0: 4 bytes 1: 8 bytes ro ro 0b 5 eeprom emulation0: normal operation (i 2 c interface used) 1: pdi emulates eeprom (i 2 c not used) note: must be written as 0. ro ro 0b 4:1 reserved ro ro 0b 0 ecat write enable 0: write requests are disabled 1: write requests are enabled (see note 24 ) r/w ro 0b bits description ecat type pdi type default downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 263 lan9252 12.14.50 eeprom address register note: write access depends upon the assignment of the eepr om interface (ecat/pdi). write access is gener- ally blocked if the eeprom interface is busy ( busy bit of eeprom control/status register = 1) note: ethercat controls the si i eeprom interface if the pdi eeprom control bit of the eeprom configuration register is 0 and the access to eeprom bit of the eeprom pdi access state register is 0. otherwise, pdi controls the eeprom interface. note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 12.14.51 eeprom data register note: write access depends upon the assignment of the eepr om interface (ecat/pdi). write access is gener- ally blocked if the eeprom interface is busy ( busy bit of eeprom control/status register = 1) note: ethercat controls the si i eeprom interface if the pdi eeprom control bit of the eeprom configuration register is 0 and the access to eeprom bit of the eeprom pdi access state register is 0. otherwise, pdi controls the eeprom interface. note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. offset: 0504h-0507h size: 32 bits bits description ecat type pdi type default 31:0 eeprom address bit 0: first word (16-bit) bit 1: second word ..... note: actually used eepr om address bits: [9:0]: eeprom size up to 16kbit [17:0]: eeprom size 32kbit - 4mbit [31:0]: eeprom emulation r/w r/w 00000000h offset: 0508h-050bh size: 32 bits bits description ecat type pdi type default 31:16 eeprom read data data to be read from eeprom, higher bytes ro ro 0000h 15:0 eeprom read/write data data to be read from eeprom, lower bytes or data to be written to eeprom. r/w r/w 0000h downloaded from: http:///
lan9252 ds00001909a-page 264 ? 2015 microchip technology inc. 12.14.52 mii management control/status register note 25: write access depends upon the assignment of the mi interface (ecat/pdi). write access is generally blocked if the mii interface is busy ( busy bit of mii management control/status register = 1) offset: 0510h-0511h size: 16 bits bits description ecat type pdi type default 15 busy 0: mi control state machine is idle 1: mi control state machine is active ro ro 0b 14 command error 0: last command was successful 1: invalid command or write command without write enable note: cleared with a valid command or by writing 00 to command register . ro ro 0b 13 read error 0: no read error 1: read error occurred (phy or register bi available) note: cleared by writing this register. r/w note 25 r/w note 25 0b 12:10 reserved ro ro 0b 9:8 command register write: initiate command. read: currently executed command see note 26 . commands: 00: no command / mi idle (clear error bits) 01: read 10: write 11: reserved (do not issue) r/w note 25 r/w note 25 00b 7:3 phy address offset ro ro 00000b 2 mi link detection (link configuration, lin k detection, registers phy port status registers ) 0: not available 1: mi link detection active ro ro 0b note 27 1 management interface control 0: ecat control only 1: mpdi control possible ( mii management ecat access state register and mii management pdi access state register ) ro ro 1b 0 write enable 0: write disabled 1: write enabled note: this bit is always 1 if pdi has mi control. (see note 28 ) r/w note 25 ro 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 265 lan9252 note 26: command register bits (9:8) are self-clearing after the command is executed (busy ends). writing 00 to the command register bits will also clear the error bi ts 14:13 of this register. the command register bits (9:8) are cleared after the command is executed. note 27: the default value of this field can be configured via eeprom. this bit will be 0 and mi link detection disabled until the device is successfully c onfigured from eeprom. the eeprom settin g for mi link detection is only taken at the first eeprom loading after power-on re set. changing the eeprom and manually reloading it will not affect the mi link detection enable status, even if the eeprom could not be read initially. refer to section 12.8, "eeprom confi gurable registers," on page 201 for additional information. note 28: write enable bit 0 is self-clearing at the sof of the next frame (or end of the pdi access). note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 12.14.53 phy address register note 29: write access depends upon the assignment of the mi interface (ecat/pdi). write access is generally blocked if the mii interface is busy ( busy bit of mii management control/status register = 1) 12.14.54 phy register address register note 30: write access depends upon the assignment of the mi interface (ecat/pdi). write access is generally blocked if the mii interface is busy ( busy bit of mii management control/status register = 1) offset: 0512h size: 8 bits bits description ecat type pdi type default 7:5 reserved write 0. ro ro 000b 4:0 phy address r/w note 29 r/w note 29 00000b offset: 0513h size: 8 bits bits description ecat type pdi type default 7:5 reserved write 0. ro ro 000b 4:0 address of phy register to be read/written r/w note 30 r/w note 30 00000b downloaded from: http:///
lan9252 ds00001909a-page 266 ? 2015 microchip technology inc. 12.14.55 phy data register note 31: write access depends upon the assignment of the mi interface (ecat/pdi). write access is generally blocked if the mii interface is busy ( busy bit of mii management control/status register = 1) note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 12.14.56 mii management ecat access state register note 32: write access only possible if the access to mii management (pdi) bit of the mii management pdi access state register is 0. offset: 0514h-0515h size: 16 bits bits description ecat type pdi type default 15:0 phy read/write data r/w note 31 r/w note 31 0000h offset: 0516h size: 8 bits bits description ecat type pdi type default 7:1 reserved write 0. ro ro 0000000b 0 access to mii management (ecat) 0: ecat enables pdi takeover of mii management control 1: ecat claims exclusive access to mii management r/w note 32 ro 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 267 lan9252 12.14.57 mii management pdi access state register note 33: write access to the access to mii management (pdi) bit of this register is only possible if the force pdi access state bit of this register is 0 and the access to mii management (ecat) bit of the mii management ecat access state register is 0. 12.14.58 phy port status registers there are 4 8-bit phy port status registers, each with unique address offsets as shown above. the variable x is used in the following bit descriptions to represent ports 0-3. offset: 0517h size: 8 bits bits description ecat type pdi type default 7:2 reserved write 0. ro ro 000000b 1 force pdi access state 0: do not change access to mii management (pdi) bit 1: reset access to mii management (pdi) bit r/w ro 0b 0 access to mii management (pdi) 0: ecat has access to mii management 1: pdi has access to mii management ro r/w note 33 0b offset: 0518h-051bh port 0: 0518h port 1: 0519h port 2: 051ah port 3: 051bh size: 8 bits bits description ecat type pdi type default 7:6 reserved write as 0. ro ro 00b 5 port x lost link counter 0: no update 1: phy configuration was updated note: cleared by writing any value to at least one of the phy port status registers . r/wc note 34 r/wc note 34 0b 4 port x link partner error 0: no error detected 1: link partner error ro ro 0b 3 port x read error 0: no read error detected 1: read error has occurred note: cleared by writing any value to at least one of the phy port status registers . r/wc note 34 r/wc note 34 0b downloaded from: http:///
lan9252 ds00001909a-page 268 ? 2015 microchip technology inc. note 34: write access depends upon the assignment of the mi interface (ecat/pdi). note: port 3 is not used. 12.14.59 fmmu[2:0] registers the device includes 3 fmmus. each fmmu is described in 16 bytes, starting at 0600h. table 12-16 details the base address for each fmmu. the subsequent fmmu registers wil l be referenced as an offset from these various base addresses. the variable x is used in the following descriptions to represent fmmus 0 through 2. 12.14.59.1 fmmu x logical start address register note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 2 port x link status error 0: no error 1: link error, link inhibited ro ro 0b 1 port x link status (100 mbit/s, full-duplex, auto-negotiation) 0: no link 1: link detected ro ro 0b 0 port x physical link (phy status register 1.2) 0: no physical link 1: physical link detected ro ro 0b table 12-16: fmmu x base addresses fmmu base address 0 0600h 1 0610h 2 0620h offset: fmmu x base address +0h-3h size: 32 bits bits description ecat type pdi type default 31:0 logical start address logical start address within the ethercat address space. r/w ro 00000000h bits description ecat type pdi type default downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 269 lan9252 12.14.59.2 fmmu x length register note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 12.14.59.3 fmmu x logical start bit register 12.14.59.4 fmmu x logical stop bit register offset: fmmu x base address +4h-5h size: 16 bits bits description ecat type pdi type default 15:0 length offset from the first logical fmmu byte to the last fmmu byte + 1 (e.g., if two bytes are used, then this parameter shall contain 2). r/w ro 0000h offset: fmmu x base address +6h size: 8 bits bits description ecat type pdi type default 7:3 reserved write as 0. ro ro 00000b 2:0 logical start bit logical starting bit that shall be mapped (bits are counted from least significant bit (0) to most significant bit (7)). r/w ro 000b offset: fmmu x base address +7h size: 8 bits bits description ecat type pdi type default 7:3 reserved write as 0. ro ro 00000b 2:0 logical stop bit last logical bit that shall be mapped (bits are counted from least significant bit (0) to most significant bit (7)). r/w ro 000b downloaded from: http:///
lan9252 ds00001909a-page 270 ? 2015 microchip technology inc. 12.14.59.5 fmmu x physical start address register note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 12.14.59.6 fmmu x physical start bit register 12.14.59.7 fmmu x type register offset: fmmu x base address +8h-9h size: 16 bits bits description ecat type pdi type default 15:0 physical start address (mapped to logical start address) r/w ro 0000h offset: fmmu x base address +ah size: 8 bits bits description ecat type pdi type default 7:3 reserved write as 0. ro ro 00000b 2:0 physical start bit physical starting bit as target of logical start bit mapping (bits are counted from least significant bit (0) to most signi ficant bit (7)). r/w ro 000b offset: fmmu x base address +bh size: 8 bits bits description ecat type pdi type default 7:2 reserved write as 0. ro ro 000000b 1 write access mapping 0: ignore mapping for write accesses 1: use mapping for write accesses r/w ro 0b 0 read access mapping 0: ignore mapping for read accesses 1: use mapping for read accesses r/w ro 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 271 lan9252 12.14.59.8 fmmu x activate register 12.14.59.9 fmmu x reserved register note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. offset: fmmu x base address +ch size: 8 bits bits description ecat type pdi type default 7:1 reserved write as 0. ro ro 0000000b 0 fmmu activation 0: fmmu x deactivated 1: fmmu x activated. fmmu x checks logical addressed blocks to be mapped according to the configured mapping. r/w ro 0b offset: fmmu x base address +dh-fh size: 24 bits bits description ecat type pdi type default 23:0 reserved write as 0. ro ro 000000h downloaded from: http:///
lan9252 ds00001909a-page 272 ? 2015 microchip technology inc. 12.14.60 syncmanager[3:0] registers the device includes 4 syncmanagers. each syncmanager is described in 8 bytes, starting at 0800h. table 12-17 details the base address for each syncmanager. the subsequent sync manager registers will be referenced as an offset from these various base addresses. the variable x is used in the following descriptions to represent syncmanagers 0 through 3. 12.14.60.1 syncmanager x physical start address register note 35: this register can only be wr itten if the corresponding sync manager is disabled via the syncmanager enable/disable bit of the syncmanager x activate register . note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 12.14.60.2 syncmanager x length register note 36: this register can only be written if syncmanager x is disabled via the syncmanager enable/disable bit of the syncmanager x activate register . note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. table 12-17: syncmanager x base addresses syncmanager base address 0 0800h 1 0808h 2 0810h 3 0818h offset: syncmanager x base address +0h-1h size: 16 bits bits description ecat type pdi type default 15:0 physical start address specifies the first byte that will be handled by syncmanager x . r/w note 35 ro 0000h offset: syncmanager x base address +2h-3h size: 16 bits bits description ecat type pdi type default 15:0 length number of bytes assigned to syncmanager x . (this field shall be greater than 1, otherwise the sy ncmanager is not activated. if set to 1, only watchdog trigger is generated, if configured.) r/w note 36 ro 0000h downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 273 lan9252 12.14.60.3 syncmanager x control register note 37: this register can only be written if syncmanager x is disabled via the syncmanager enable/disable bit of the syncmanager x activate register . offset: syncmanager x base address +4h size: 8 bits bits description ecat type pdi type default 7 reserved write as 0. ro ro 0b 6 watchdog trigger enable 0: disabled 1: enabled r/w note 37 ro 0b 5 interrupt in pdi e vent request register 0: disabled 1: enabled r/w note 37 ro 0b 4 interrupt in ecat e vent request register 0: disabled 1: enabled r/w note 37 ro 0b 3:2 direction00: read: ecat read access, pdi write access 01: write: ecat write access, pdi read access 10: reserved 11: reserved r/w note 37 ro 00b 1:0 operation mode 00: buffered (3 buffer mode) 01: reserved 10: mailbox (single buffer mode) 11: reserved r/w note 37 ro 00b downloaded from: http:///
lan9252 ds00001909a-page 274 ? 2015 microchip technology inc. 12.14.60.4 syncmanager x status register offset: syncmanager x base address +5h size: 8 bits bits description ecat type pdi type default 7 write buffer in use (opened) ro ro 0b 6 read buffer in use (opened) ro ro 0b 5:4 buffer status (last written buffer) buffered mode: 00: 1. buffer 01: 2. buffer 10: 3. buffer 11: no buffer written mailbox mode: reserved ro ro 11b 3 mailbox status mailbox mode: 0: mailbox empty 1: mailbox full buffered mode: reserved ro ro 0b 2 reserved write as 0. ro ro 0b 1 interrupt read0: interrupt cleared after first byte of buffer was written 1: interrupt after buffer was completely and successfully read ro ro 0b 0 interrupt write 0: interrupt cleared after first byte of buffer was read 1: interrupt after buffer was completely and successfully written ro ro 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 275 lan9252 12.14.60.5 syncmanager x activate register note: reading this register from pdi in all syncmana gers which have changed activation clears the syncman- ager x activation register changed bit in the al event request register . offset: syncmanager x base address +6h size: 8 bits bits description ecat type pdi type default 7 latch event pdi 0: no 1: generate latch events if pdi issues a buffer exchange or if pdi accesses buffer start address. r/w ro 0b 6 latch event ecat 0: no 1: generate latch event if ethe rcat master issues a buffer exchange. r/w ro 0b 5:2 reserved write as 0. ro ro 0000b 1 repeat request a toggle of repeat request indicates that a mailbox retry is needed (primarily used in conjunction with ecat read mailbox) r/w ro 0b 0 syncmanager enable/disable 0: disable: access to memory without syncmanager control 1: enable: syncmanager is active and controls memory area set in configuration. r/w ro 0b downloaded from: http:///
lan9252 ds00001909a-page 276 ? 2015 microchip technology inc. 12.14.60.6 syncmanager x pdi control register 12.14.61 receive time port 0 register note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. offset: syncmanager x base address +7h size: 8 bits bits description ecat type pdi type default 7:2 reserved write as 0. ro ro 000000b 1 repeat ack if this is set to the same value as repeat request , the pdi acknowledges the execution of a previous set repeat request. ro r/w 0b 0 deactivate syncmanager x read: 0: normal operation, syncmanager x activated 1: syncmanager x deactivated and reset syncmanager x locks access to memory area write: 0: activate syncmanager 1: request syncmanager deactivation ro r/w 0b offset: 0900h-0903h size: 32 bits bits description ecat type pdi type default 31:0 write: a write access to register 0900h with bwr, apwr (any address) or fpwr (configured address) latches the local time of the beginning of the receive frame (start first bit of preamble) at each port. read: local time of the beginning of the last receive frame containing a write access to this register. note: the time stamps cannot be read in the same frame in which this register was written. r/w ro undefined downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 277 lan9252 12.14.62 receive time port 1 register note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 12.14.63 receive time port 2 register note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. offset: 0904h-0907h size: 32 bits bits description ecat type pdi type default 31:0 local time of the beginning of a frame (start first bit of preamble) received at port 1 containing a bwr/apwr or fpwr to the receive time port 0 register . ro ro undefined offset: 0908h-090bh size: 32 bits bits description ecat type pdi type default 31:0 local time of the beginning of a frame (start first bit of preamble) received at port 2 containing a bwr/apwr or fpwr to the receive time port 0 register . ro ro undefined downloaded from: http:///
lan9252 ds00001909a-page 278 ? 2015 microchip technology inc. 12.14.64 system time register note 38: when writing via ecat, the control loop is triggered to process the new value. note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 12.14.65 receive time ecat processing unit register note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. offset: 0910h-0917h size: 64 bits bits description ecat type pdi type default 63:0 ecat read access: local copy of the system time when the frame passed the refer- ence clock (i.e., including system time delay). time latched at beginning of the frame (ethernet sof delimiter). pdi read access: local copy of the system time. time latched when reading first byte (0910h). ro ro 00000000h 00000000h 31:0 write access: written value will be compared wit h the local copy of the system time. the result is an input to the time control loop. note: written value will be compared at the end of the frame with the latched (sof) loca l copy of the system time if at least the first byte (0910h) was written. w note 38 ro 00000000h offset: 0918h-091fh size: 64 bits bits description ecat type pdi type default 63:0 local time of the beginning of a frame (start first bit of preamble) received at the ecat processing unit containing a write access to receive time port 0 register (0900h). note: if port 0 is open, this register reflects the receive time port 0 register as a 64-bit value. ro ro 00000000h 00000000h downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 279 lan9252 12.14.66 system time offset register note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 12.14.67 system time delay register note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 12.14.68 system time difference register note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. offset: 0920h-0927h size: 64 bits bits description ecat type pdi type default 63:0 difference between local time and system time. offset is added to local time. local time of the beginning of a frame (start first bit of preamble) received at the ecat processing unit containing a write access to receive time port 0 register (0900h). note: if port 0 is open, this register reflects the receive time port 0 register as a 64-bit value. r/w ro 00000000h 00000000h offset: 0928h-092bh size: 32 bits bits description ecat type pdi type default 31:0 delay between reference clock and the esc. r/w ro 00000000h offset: 092ch-092fh size: 32 bits bits description ecat type pdi type default 31 0: local copy of system time greater than or equal to received system time 1: local copy of system time smaller than received system time ro ro 0b 30:0 mean difference between local copy of system time and received system time values. ro ro 00000000h downloaded from: http:///
lan9252 ds00001909a-page 280 ? 2015 microchip technology inc. 12.14.69 speed counter start register note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 12.14.70 speed counter diff register note: the clock deviation after system time difference has settled at a low value can be calculated as follows: deviation = speed counter diff / 5(speed counter start + speed counter diff + 2)(speed counter start - speed counter diff + 2) note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. offset: 0930h-0931h size: 16 bits bits description ecat type pdi type default 15 reserved write as 0. ro ro 0b 14:0 bandwidth for adjustment of loca l copy of system time (larger values -> smaller bandwidth and smoother adjust ment). a write access resets the system time difference register and speed counter diff register . valid range: 0080h-3fffh. r/w ro 1000h offset: 0932h-0933h size: 16 bits bits description ecat type pdi type default 15:0 representation of the deviation between local clock period and reference clocks clock period (representation: twos compli- ment). valid range: +/-( speed counter start register -7fh). ro ro 0000h downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 281 lan9252 12.14.71 system time difference filter depth register 12.14.72 speed counter filter depth register offset: 0934h size: 8 bits bits description ecat type pdi type default 7:4 reserved ro ro 0h 3:0 filter depth for averaging the received system time deviation. note: a write access resets the system time difference register . r/w ro 4h offset: 0935h size: 8 bits bits description ecat type pdi type default 7:4 reserved ro ro 0h 3:0 filter depth for averaging the clock period deviation. note: a write access resets the internal speed counter filter. r/w ro ch downloaded from: http:///
lan9252 ds00001909a-page 282 ? 2015 microchip technology inc. 12.14.73 cyclic unit control register offset: 0980h size: 8 bits bits description ecat type pdi type default 7:6 reserved write as 0. ro ro 00b 5 latch in unit 1 0: ecat controlled 1: pdi controlled note: latch interrupt is routed to ecat/pdi depending on this setting. r/w ro 0b 4 latch in unit 0 0: ecat controlled 1: pdi controlled note: always 1 (pdi controlled) is system time is pdi con- trolled. latch interrupt is routed to ecat/pdi depend- ing on this setting. r/w ro 0b 3:1 reserved write as 0. ro ro 000b 0 sync out unit control 0: ecat controlled 1: pdi controlled r/w ro 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 283 lan9252 12.14.74 activation register note: writes to this register depend on the sync out unit control bit of the cyclic unit control register . offset: 0981h size: 8 bits bits description ecat type pdi type default 7 syncsignal debug pulse (vasili bit) 0: deactivated 1: immediately generate a single debug ping on sync0 and sync1 according to bits 2 and 1 of this register. r/w r/w 0b 6 near future configuration (approx.) 0: 1/2 dc width future (2 31 ns or 2 63 ns) 1: 2.1 sec future (2 31 ns) r/w r/w 0b 5 start time plausibility check 0: disabled. syncsignal generation if start time is reached. 1: immediate syncsignal generation if start time is outside near future configuration (approx.) . r/w r/w 0b 4 extension of start ti me cyclic operation ( start time cyclic operation register ) 0: no extension 1: extend 32-bit written start time to 64-bit r/w r/w 0b 3 auto-activation (by writing start time cyclic operation register ) 0: disabled 1: auto-activation enabled. sync out unit activation is set auto- matically after start time is written. r/w r/w 0b 2 sync1 generation 0: deactivated 1: sync1 pulse is generated r/w r/w 0b 1 sync0 generation 0: deactivated 1: sync0 pulse is generated r/w r/w 0b 0 sync out unit activation0: deactivated 1: activated note: write 1 after start time is written r/w r/w 0b downloaded from: http:///
lan9252 ds00001909a-page 284 ? 2015 microchip technology inc. 12.14.75 pulse length of syncsignals register note 39: the default value of this field can be configured via eeprom. refer to section 12.8, "eeprom configu- rable registers," on page 201 for additional information. note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 12.14.76 activation status register offset: 0982h-0983h size: 16 bits bits description ecat type pdi type default 15:0 pulse length of syncsignals (in units of 10ns) a value of 0 is used for acknowledge mode: syncsignal will be cleared by reading the sync0 status register / sync1 status register . ro ro 0000h note 39 offset: 0984h size: 8 bits bits description ecat type pdi type default 7:3 reserved ro ro 00000b 2 start time cyclic operation ( start time cyclic operation regis- ter ) plausibility check result when sync out unit was activated. 0: start time was within near future 1: start time was out of near future ro ro 0b 1 sync1 activation state 0: first sync1 pulse is not pending 1: first sync1 pulse is pending ro ro 0b 0 sync0 activation state 0: first sync0 pulse is not pending 1: first sync0 pulse is pending ro ro 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 285 lan9252 12.14.77 sync0 status register 12.14.78 sync1 status register 12.14.79 start time cyclic operation register note: writes to this register depend on the sync out unit control bit of the cyclic unit control register . it is only writable if sync out unit control is 0. note: when the auto-activation bit of the activation register is 1: the upper 32 bits are automatically extended if only the lower 32 bits are written within one frame. note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. offset: 098eh size: 8 bits bits description ecat type pdi type default 7:1 reserved ro ro 0000000b 0 sync0 state for acknowledge mode sync0, in acknowledge mode, is cleared by reading this regis- ter from pdi. use only in acknowledge mode. ro ro 0b offset: 098fh size: 8 bits bits description ecat type pdi type default 7:1 reserved ro ro 0000000b 0 sync1 state for acknowledge mode sync1, in acknowledge mode, is cleared by reading this regis- ter from pdi. use only in acknowledge mode. ro ro 0b offset: 0990h-0997h size: 64 bits bits description ecat type pdi type default 63:0 write: start time (system time) of cyclic operation in ns. read: system time of next sync0 pulse in ns. r/w r/w 00000000h 00000000h downloaded from: http:///
lan9252 ds00001909a-page 286 ? 2015 microchip technology inc. 12.14.80 next sync1 pulse register note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 12.14.81 sync0 cycle time register note: writes to this register depend on the sync out unit control bit of the cyclic unit control register . note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 12.14.82 sync1 cycle time register note: writes to this register depend on the sync out unit control bit of the cyclic unit control register . note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. offset: 0998h-099fh size: 64 bits bits description ecat type pdi type default 63:0 system time of next sync1 pulse in ns. ro ro 00000000h 00000000h offset: 09a0h-09a3h size: 32 bits bits description ecat type pdi type default 31:0 time between two consecut ive sync0 pulses in ns. a value of 0 indicates single shot mode - generate only one sync0 pulse. r/w r/w 00000000h offset: 09a4h-09a7h size: 32 bits bits description ecat type pdi type default 31:0 time between sync1 pulses and sync0 pulse in ns. r/w r/w 00000000h downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 287 lan9252 12.14.83 latch0 control register note: writes to this register depend on the latch in unit 0 bit of the cyclic unit control register . 12.14.84 latch1 control register note: writes to this register depend on the latch in unit 1 bit of the cyclic unit control register . offset: 09a8h size: 8 bits bits description ecat type pdi type default 7:2 reserved write as 0. ro ro 000000b 1 latch0 negative edge 0: continuous latch active 1: single event (only first event active) r/w r/w 0b 0 latch0 positive edge 0: continuous latch active 1: single event (only first event active) r/w r/w 0b offset: 09a9h size: 8 bits bits description ecat type pdi type default 7:2 reserved write as 0. ro ro 000000b 1 latch1 negative edge 0: continuous latch active 1: single event (only first event active) r/w r/w 0b 0 latch1 positive edge 0: continuous latch active 1: single event (only first event active) r/w r/w 0b downloaded from: http:///
lan9252 ds00001909a-page 288 ? 2015 microchip technology inc. 12.14.85 latch0 status register 12.14.86 latch1 status register offset: 09aeh size: 8 bits bits description ecat type pdi type default 7:3 reserved write as 0. ro ro 00000b 2 latch0 pin state ro ro 0b 1 event latch0 negative edge 0: negative edge not detected or continuous mode 1: negative edge detected in single event mode only. note: flag cleared by reading the latch0 time negative edge register . ro ro 0b 0 event latch0 positive edge 0: positive edge not detected or continuous mode 1: positive edge detected in single event mode only. note: flag cleared by reading the latch0 time positive edge register . ro ro 0b offset: 09afh size: 8 bits bits description ecat type pdi type default 7:3 reserved write as 0. ro ro 00000b 2 latch1 pin state ro ro 0b 1 event latch1 negative edge 0: negative edge not detected or continuous mode 1: negative edge detected in single event mode only. note: flag cleared by reading the latch1 time negative edge register . ro ro 0b 0 event latch1 positive edge 0: positive edge not detected or continuous mode 1: positive edge detected in single event mode only. note: flag cleared by reading the latch1 time positive edge register . ro ro 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 289 lan9252 12.14.87 latch0 time positive edge register note: register bits [63:8] are internally latched (ecat/pdi independently) when bits [7:0] are read, which guaran- tees reading a consistent value. clearing the event latch0 positive edge bit of the latch0 status reg- ister depends upon setting of the latch in unit 0 bit of the cyclic unit control register . note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 12.14.88 latch0 time negative edge register note: register bits [63:8] are internally latched (ecat/pdi independently) when bits [7:0] are read, which guaran- tees reading a consistent value. clearing the event latch0 negative edge bit of the latch0 status reg- ister depends upon setting of the latch in unit 0 bit of the cyclic unit control register . note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. offset: 09b0h-09b7h size: 64 bits bits description ecat type pdi type default 63:0 this register captures the syst em time at the positive edge of the latch0 signal. note: reading this register clears the event latch0 posi- tive edge bit of the latch0 status register ro ro 00000000h 00000000h offset: 09b8h-09bfh size: 64 bits bits description ecat type pdi type default 63:0 this register captures the syst em time at the negative edge of the lacth0 signal. note: reading this register clears the event latch0 neg- ative edge bit of the latch0 status register ro ro 00000000h 00000000h downloaded from: http:///
lan9252 ds00001909a-page 290 ? 2015 microchip technology inc. 12.14.89 latch1 time positive edge register note: register bits [63:8] are internally latched (ecat/pdi independently) when bits [7:0] are read, which guaran- tees reading a consistent value. clearing the event latch1 positive edge bit of the latch1 status reg- ister depends upon setting of the latch in unit 1 bit of the cyclic unit control register . note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 12.14.90 latch1 time negative edge register note: register bits [63:8] are internally latched (ecat/pdi independently) when bits [7:0] are read, which guaran- tees reading a consistent value. clearing the event latch1 negative edge bit of the latch1 status reg- ister depends upon setting of the latch in unit 1 bit of the cyclic unit control register . note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. offset: 09c0h-09c7h size: 64 bits bits description ecat type pdi type default 63:0 this register captures the syst em time at the positive edge of the latch1 signal. note: reading this register clears the event latch1 posi- tive edge bit of the latch1 status register ro ro 00000000h 00000000h offset: 09c8h-09cfh size: 64 bits bits description ecat type pdi type default 63:0 this register captures the syst em time at the negative edge of the latch1 signal. note: reading this register clears the event latch1 neg- ative edge bit of the latch1 status register ro ro 00000000h 00000000h downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 291 lan9252 12.14.91 ethercat buffer change event time register note: register bits [31:8] are internally latched (ecat/pdi independently) when bits [7:0] are read, which guaran- tees reading a consistent value. note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 12.14.92 pdi buffer start time event register note: register bits [31:8] are internally latched (ecat/pdi independently) when bits [7:0] are read, which guaran- tees reading a consistent value. note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 12.14.93 pdi buffer chan ge event time register note: register bits [31:8] are internally latched (ecat/pdi independently) when bits [7:0] are read, which guaran- tees reading a consistent value. note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. offset: 09f0h-09f3h size: 32 bits bits description ecat type pdi type default 31:0 this register captures the local time of the beginning of the frame which causes at least one syncmanager to assert an ecat event. ro ro 00000000h offset: 09f8h-09fbh size: 32 bits bits description ecat type pdi type default 31:0 this register captures the local time when at least one syncman- ager asserts a pdi buffer start event. ro ro 00000000h offset: 09fch-09ffh size: 32 bits bits description ecat type pdi type default 31:0 this register captures the local time when at least one syncman- ager asserts a pdi buffer change event. ro ro 00000000h downloaded from: http:///
lan9252 ds00001909a-page 292 ? 2015 microchip technology inc. 12.14.94 product id register note 40: the value of ss is 0, 0, link_pol_strap_mii , tx_shift_strap[1:0] , eeprom_size_strap , chip_mode_strap[1:0] . the value of rrrr is the current silicon revision. note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 12.14.95 vendor id register note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 12.14.96 digital i/o output data register note: this register is bit-writable (using logical addressing). note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. offset: 0e00h-0e07h size: 64 bits bits description ecat type pdi type default 63:0 product id ro ro 0000h 00 ss h 9252h rrrr h note 40 offset: 0e08h-0e0fh size: 64 bits bits description ecat type pdi type default 63:32 reserved ro ro 00000000h 31:0 vendor id ro ro 000004d8h (microchip) offset: 0f00h-0f01h size: 16 bits bits description ecat type pdi type default 15:0 output data r/w ro 0000h downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 293 lan9252 12.14.97 general purpose output register note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 12.14.98 general purpose input register note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 12.14.99 user ram note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. offset: 0f10h-0f11h size: 16 bits bits description ecat type pdi type default 15:0 general purpose output data r/w r/w 0000h offset: 0f18h-0f19h size: 16 bits bits description ecat type pdi type default 15:0 general purpose input data ro ro 0000h offset: 0f80h-0fffh size: 128 bytes bits description ecat type pdi type default - user ram (128 bytes) r/w r/w undefined downloaded from: http:///
lan9252 ds00001909a-page 294 ? 2015 microchip technology inc. 12.14.100 digital i/o input data register note: this register is part of the process ram address space. the process ram is also directly addressable via the ethercat process ram read data fifo (ecat_pram_rd_data) and ethercat process ram write data fifo (ecat_pram_wr_data) . note: process data ram is only accessible if eeprom was correctly loaded ( pdi operational/eeprom loaded correctly bit of esc dl status register = 1) note: digital i/o input data is written into the process data ram at these addresses if a digital i/o pdi with inputs is configured. note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. 12.14.101 process data ram note: process data ram is only accessible if eeprom was correctly loaded ( pdi operational/eeprom loaded correctly bit of esc dl status register = 1) note: for ethercat core csr registers longer than one by te, the lsb has the lowest address and the msb the highest address. offset: 1000h-1001h size: 16 bits bits description ecat type pdi type default 15:0 input data r/w r/w undefined offset: 1000h-1fffh size: 4 kbytes bits description ecat type pdi type default - process data ram (4 kbytes) r/w r/w undefined downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 295 lan9252 13.0 eeprom interface the device contains an i 2 c master controller, which uses the eescl and eesda pins. eescl and eesda require an external pull-up resistor. both 1 byte and 2 byte address ed eeproms are supported. the size is determined by the eeprom_size_strap . 13.1 i 2 c interface timing requirements this section specifies the i 2 c master interface input and output timings. the i 2 c master interface runs in fast-mode with a rate of 148.8 khz. note 41: these values provide 400 ns of margin compared to the i 2 c fast-mode specification. note 42: these values provide ~2100 ns of margin compared to the i 2 c fast-mode specification. note 43: these values provide 300 ns of setup margin and 400 ns of hold margin compared to the i 2 c fast-mode specification. figure 13-1: i 2 c master timing diagram table 13-1: i 2 c master timing values symbol description min typ max units f scl eescl clock frequency - 148.8 - khz t high eescl high time 3.0 - - ? s t low eescl low time 3.0 - - ? s t r rise time of eesda and eescl -3 0 0n s t f fall time of eesda and eescl -3 0 0n s t su;sta setup time (provided to slave) of eescl high before eesda output falling for repeated start condition 1000 note 41 --n s t hd;sta hold time (provided to slave) of eescl after eesda output fall- ing for start or repeated start condition 1000 note 41 --n s t su;dat;in setup time (from slave) eesda input before eescl rising 200 note 42 --n s t hd;dat;in hold time (from slave) of eesda input after eescl falling 0 - - ns t su;dat;out setup time (provided to slave) eesda output before eescl rising 400 note 42 --n s t hd;dat;out hold time (provided to slave) of eesda output after eescl fall- ing 400 note 42 --n s t su;sto setup time (provided to slave) of eescl high before eesda output rising for stop condition 1000 note 41 --n s eesda (out) eescl s p sr t f t r t hd;sta t hd;dat;in t su;dat;in t su;sta t su;sto eesda (in) t high t low t hd;dat;out t su;dat;out downloaded from: http:///
lan9252 ds00001909a-page 296 ? 2015 microchip technology inc. 14.0 chip mode configuration the mode of the chip is controlled by the chip_mode_strap[1:0] ( chip_mode1 / chip_mode0 ) hard-strap as follows: once the mode of the chip is selected, the process data inte rface (pdi) in use is selected by the pdi control register (0x0140). the valid choices are as follows: note: the mode of the chip as selected by the chip_mode_strap[1:0] hard-strap is not affected by the pdi selec- tion. note: due to pin sharing, when the device is in 3 port mode, the only usable interface is spi. 14.1 hbi sub-configuration the pdi configuration register (0x0150) is used for the hbi configuration straps as shown in table 12- 3, "ethercat core eeprom configurable registers" . the pdi configuration register (0x0150) is initialized fr om the contents of the eeprom. table 14-1: chip mode selection chip_mode[1:0] mode 00 2 port mode. port 0 = phy a, port 1 = phy b 01 reserved 10 3 port downstream mode. port 0 = ph y a, port 1 = phy b, port 2 = mii 11 3 port upstream mode. port 0 = mii, port 1 = phy b, port 2 = phy a table 14-2: pdi mode selection pdi_select pdi mode 0x04 dig i/o 0x80 spi 0x88 hbi multiplexed 1 phase 8-bit 0x89 hbi multiplexed 1 phase 16-bit 0x8a hbi multiplexed 2 phase 8-bit 0x8b hbi multiplexed 2 phase 16-bit 0x8c hbi indexed 8-bit 0x8d hbi indexed 16-bit others reserved downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 297 lan9252 15.0 general purpose timer & free-running clock this chapter details the general purpos e timer (gpt) and the free-running clock. 15.1 general purpose timer the device provides a 16-bit programm able general purpose timer that can be used to generate periodic system inter- rupts. the resolution of this timer is 100 s. the gpt loads the general purpose timer count register (gpt_cnt) with the value in the general purpose timer pre-load (gpt_load) field of the general purpose timer confi guration register (gpt_cfg) when the general pur- pose timer enable (timer_en) bit of the general purpose timer configuration register (gpt_cfg) is asserted (1). on a chip-level reset or when the general purpose timer enable (timer_en) bit changes from asserted (1) to de- asserted (0), the general purpose timer pre-load (gpt_load) field is initialized to ffffh. the general purpose timer count register (gpt_cnt) is also initialized to ffffh on reset. once enabled, the gpt counts down until it reaches 0000h. at 0000h, the counter wraps around to ffffh, asserts the gp timer (gpt_int) interrupt status bit in the interrupt status register (int_sts) , asserts the irq interrupt (if gp timer interrupt enable (gpt_int_en) is set in the interrupt enable register (int_en) ) and continues counting. gp timer (gpt_int) is a sticky bit. once this bit is asserted, it can only be cleared by writing a 1 to the bit. refer to section 8.2.3, "general purpose timer interrupt," on page 55 for additional informati on on the gpt interrupt. software can write a pre-load value into the general purpose timer pre-load (gpt_load) field at any time (e.g., before or after the general purpose timer enable (timer_en) bit is asserted). the general purpose timer count reg- ister (gpt_cnt) will immediately be set to the new value and continue to count down (if enabled) from that value. 15.2 free-running clock the free-running clock (frc) is a simple 32-bit up-counter that operates from a fixed 25 mhz clock. the current frc value can be read via the free running 25mhz counter register (free_run) . on assertion of a chip-level reset, this counter is cleared to zero. on de-asse rtion of a reset, the counter is incr emented once for every 25 mhz clock cycle. when the maximum count has been reached, the counter rolls over to zeros. the frc does not generate interrupts. note: the free running counter can take up to 160 ns to clear after a reset event. 15.3 general purpose timer and free-running clock registers this section details the directly addressable general purpos e timer and free-running clock related system csrs. for an overview of the entire directly addressable register map, refer to section 5.0, "register map," on page 32 . table 15-1: miscellaneous registers address register name (symbol) 08ch general purpose timer conf iguration register (gpt_cfg) 090h general purpose timer count register (gpt_cnt) 09ch free running 25mhz counter register (free_run) downloaded from: http:///
lan9252 ds00001909a-page 298 ? 2015 microchip technology inc. 15.3.1 general purpose timer configuration register (gpt_cfg) this read/write register configures the devices general purpose timer (gpt). the gpt ca n be configured to generate host interrupts at the interval defined in this register. the current value of the gpt can be monitored via the general purpose timer count register (gpt_cnt) . refer to section 15.1, "general purpose timer," on page 297 for additional information. offset: 08ch size: 32 bits bits description type default 31:30 reserved ro - 29 general purpose timer enable (timer_en) this bit enables the gpt. when set, the gpt enters the run state. when cleared, the gpt is halted. on the 1 to 0 transition of this bit, the gpt_load field of this register will be preset to ffffh. 0: gpt disabled 1: gpt enabled r/w 0b 28:16 reserved ro - 15:0 general purpose timer pre-load (gpt_load) this value is pre-loaded into the gpt. th is is the starting value of the gpt. the timer will begin decrementing from this value when enabled. r/w ffffh downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 299 lan9252 15.3.2 general purpose timer count register (gpt_cnt) this read-only register reflects the curr ent general purpose timer (gpt) value. th e register should be used in conjunc- tion with the general purpose timer configuration register (gpt_cfg) to configure and monitor the gpt. refer to section 15.1, "general purpose timer," on page 297 for additional information. offset: 090h size: 32 bits bits description type default 31:16 reserved ro - 15:0 general purpose timer current count (gpt_cnt) this 16-bit field represents the current value of the gpt. ro ffffh downloaded from: http:///
lan9252 ds00001909a-page 300 ? 2015 microchip technology inc. 15.3.3 free running 25mhz counter register (free_run) this read-only register reflects the current va lue of the free-running 25mhz counter. refer to section 15.2, "free-run- ning clock," on page 297 for additional information. offset: 09ch size: 32 bits bits description type default 31:0 free running counter (fr_cnt) this field reflects the current value of the free-running 32-bit counter. at reset, the counter starts at zero and is incremented by one every 25 mhz cycle. when the maximum c ount has been reac hed, the counter will rollover to zero and continue counting. note: the free running counter can take up to 160ns to clear after a reset event. ro 00000000h downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 301 lan9252 16.0 miscellaneous this chapter describes miscellaneous functions an d registers that are present in the device. 16.1 miscellaneous system configuration & status registers this section details the remainder of the directly addre ssable system csrs. these registers allow for monitoring and configuration of various device functions such as the chip id/revision, byte order testi ng, and hardware configuration. for an overview of the entire directly addressable register map, refer to section 5.0, "register map," on page 32 . table 16-1: miscellaneous registers address register name (symbol) 050h chip id and revision (id_rev) 064h byte order test register (byte_test) 074h hardware configuration register (hw_cfg) downloaded from: http:///
lan9252 ds00001909a-page 302 ? 2015 microchip technology inc. 16.1.1 chip id and revision (id_rev) this read-only register contains the id and revision fields for the device. note 1: default value is dependent on device revision. offset: 050h size: 32 bits bits description type default 31:16 chip id this field indicates the chip id. ro 9252 15:0 chip revision this field indicates the design revision. ro note 1 downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 303 lan9252 16.1.2 byte order test register (byte_test) this read-only register can be used to determine the byte ordering of the current configuration. byte ordering is a func- tion of the host data bus width and endianess. refer to section 9.0, "host bus interface," on page 62 for additional infor- mation on byte ordering. the byte_test register can optionally be used as a dummy read register when assuring minimum write-to-read or read-to-read timing. refer to section 9.0, "host bus interface," on page 62 for additional information. for host interfaces that are disabled during the reset state, the byte_test register can be used to determine when the device has exited the reset state. note: this register can be read while the device is in the re set or not ready / power savings states without leaving the host interface in an intermediate state. if the ho st interface is in a reset state, returned data may be invalid. however, during reset, the returned data will not match the normal valid data pattern. note: it is not necessary to read all fours bytes of this r egister. dword access rules do not apply to this register. offset: 064h size: 32 bits bits description type default 31:0 byte test (byte_test) this field reflects the current byte ordering ro 87654321h downloaded from: http:///
lan9252 ds00001909a-page 304 ? 2015 microchip technology inc. 16.1.3 hardware configuration register (hw_cfg) this register allows the configuration of various hardware features. note: this register can be read while the device is in the re set or not ready / power savings states without leaving the host interface in an intermediate state. if the ho st interface is in a reset state, returned data may be invalid. note: it is not necessary to read all fours bytes of this r egister. dword access rules do not apply to this register. offset: 074h size: 32 bits bits description type default 31:28 reserved ro - 27 device ready (ready) when set, this bit indicates that the device is ready to be accessed. upon power-up, rst# reset, retu rn from power savings stat es, ethercat chip level or module level reset, or digital reset, the host processor may interrogate this field as an indication that the device has stabilized and is fully active. this rising edge of this bit will assert the device ready (ready) bit in the interrupt status register (int_sts) and can cause an interrupt if enabled. note: with the exception of the hw_cfg, pmt_ctrl, byte_test, and reset_ctl registers, read access to any internal resources is forbidden while the ready bit is cleared. writes to any address are invalid until this bit is set. note: this bit is identical to bit 0 of the power management control register (pmt_ctrl) . ro 0b 26 reserved ro - 25 reserved ro - 24:22 reserved ro - 21:16 reserved ro - 15:14 reserved ro - 13:12 reserved ro - 11:0 reserved ro - downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 305 lan9252 17.0 jtag 17.1 jtag a ieee 1149.1 compliant tap controller suppor ts boundary scan and various test modes. the device includes an integrated jtag boundary-scan test por t for board-level testing. the interface consists of four pins ( tdo , tdi , tck and tms ) and includes a state machine, data register array, and an instruction register. the jtag pins are described in table 3-14, jtag pin descriptions, on page 28 . the jtag interface conforms to the ieee stan- dard 1149.1 - 2001 standard test access port (tap) and boundary-scan architecture . all input and output data is synchronous to the tck test clock input. tap input signals tms and tdi are clocked into the test logic on the rising edge of tck , while the output signal tdo is clocked on the falling edge. jtag pins are multiplexed with th e gpio/led and eeprom pins. the jtag functionality is selected when the test- mode pin is asserted. the implemented ieee 1149.1 instructions and their op codes are shown in ta b l e 1 7 - 1 . note: the jtag device id is 00101445h note: all digital i/o pins support ieee 1149.1 operation. analog pins and the osci / osco pins do not support ieee 1149.1 operation. table 17-1: ieee 1149.1 op codes instruction op code comment bypass 0 16'h0000 mandatory instruction bypass 1 16'hffff mandatory instruction sample/preload 16'hfff8 mandatory instruction extest 16'hffe8 mandatory instruction clamp 16'hffef optional instruction id_code 16'hfffe optional instruction highz 16'hffcf optional instruction int_dr_sel 16'hfffd private instruction downloaded from: http:///
lan9252 ds00001909a-page 306 ? 2015 microchip technology inc. 17.1.1 jtag timing requirements this section specifies the jtag timing of the device. note: timing values are with respect to an equivalent test load of 25 pf. figure 17-1: jtag timing table 17-2: jtag timing values symbol description min max units notes t tckp tck clock period 40 ns t tckhl tck clock high/low time t tckp *0.4 t tckp *0.6 ns t su tdi , tms setup to tck rising edge 5 ns t h tdi , tms hold from tck rising edge 5 ns t dov tdo output valid from tck falling edge 15 ns t doinvld tdo output invalid from tck falling edge 0 ns tck (input) tdi , tms (inputs) t tckhl t tckp t tckhl t su t h t dov tdo (output) t doinvld downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 307 lan9252 18.0 operational characteristics 18.1 absolute maximum ratings* supply voltage ( vdd12tx1 , vdd12tx2 , oscvdd12 , vddcr ) ( note 1 ) . . . . . . . . . . . . . . . . . . . . . . . . 0 v to +1.5 v supply voltage ( vdd33txrx1 , vdd33txrx2 , vdd33bias , vdd33 , vddio ) ( note 1 ) . . . . . . . . . . . . . 0 v to +3.6 v ethernet magnetics supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 v to +3.6 v positive voltage on input signal pins, with respect to ground ( note 2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . vddio + 2.0 v negative voltage on input signal pins, with respect to ground ( note 3 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 v positive voltage on osci , with respect to ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+3.6 v storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55 o c to +150 o c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150 o c lead temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . refer to jedec spec. j-std-020 hbm esd performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . jedec class 3a note 1: when powering this device from laboratory or system powe r supplies, it is important that the absolute max- imum ratings not be exceeded or device failure can result. some power supplies exhibit voltage spikes on their outputs when ac power is switched on or off. in addition, voltage transients on the ac power line may appear on the dc output. if this possibility exis ts, it is suggested to use a clamp circuit. note 2: this rating does not apply to the following pins: osci , rbias note 3: this rating does not apply to the following pins: rbias *stresses exceeding those listed in th is section could cause permanent damage to the device. this is a stress rating only. exposure to absolute maximum rating conditions for extended periods may affect device reliability. functional operation of the device at any condition exceeding those indicated in section 18.2, "operating conditions**" , section 18.5, "dc specifications" , or any other applicable section of this specif ication is not implied. note, device signals are not 5 volt tolerant. 18.2 operating conditions** supply voltage ( vdd12tx1 , vdd12tx2 , oscvdd12 , vddcr ) . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.14 v to +1.26 v analog port supply voltage ( vdd33txrx1 , vdd33txrx2 , vdd33bias , vdd33 ) . . . . . . . . . . . . . . . +3.0 v to +3.6 v i/o supply voltage ( vddio ) ( note 1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.62 v to +3.6 v ethernet magnetics supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.25 v to +3.6 v ambient operating temperature in still air (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . note 4 note 4: 0 o c to +70 o c for commercial version, -40 o c to +85 o c for industrial version, -40 o c to +105 o c for extended industrial version. extended industrial temperature range is supported with the following restrictions: - 64-qfn package: external regulator required (internal regulator disabled) and 2.5 v (typ) ethernet magnetics voltage. **proper operation of the device is guar anteed only within the ranges specified in this section. after the device has com- pleted power-up, vddio and the magnetics power supply must maintain their voltage level with 10%. varying the volt- age greater than 10% after the device has completed power-up can cause errors in device operation. note: do not drive input signals without power supplied to the device. downloaded from: http:///
lan9252 ds00001909a-page 308 ? 2015 microchip technology inc. 18.3 package thermal specifications note: thermal parameters are measured or estimated fo r devices in a multi-layer 2s2p pcb per jesd51. table 18-1: 64-pin qfn package thermal parameters parameter symbol value units comments thermal resistance junction to ambient ? ja 23.6 c/w measured in still air thermal resistance junction to bottom of case ? jt 0.1 c/w measured in still air thermal resistance junction to top of case ? jc 1.8 c/w airflow 1 m/s table 18-2: 64-pin tqfp-ep package thermal parameters parameter symbol value units comments thermal resistance junction to ambient ? ja 29.0 c/w measured in still air thermal resistance junction to bottom of case ? jt 0.3 c/w measured in still air thermal resistance junction to top of case ? jc 12.8 c/w airflow 1 m/s table 18-3: maximum power dissipation mode maximum power (mw) internal regulator disabled , 2.5 v ethernet magnetics 568 internal regulator disabled , 3.3 v ethernet magnetics 640 internal regulator enabled, 2.5 v ethernet magnetics 749 internal regulator enabled, 3.3 v ethernet magnetics 821 downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 309 lan9252 18.4 current consumption and power consumption this section details the devices typical supply current consumption and power dissipation for 100base-tx and power management modes of operation with the internal regulator enabled and disabled. 18.4.1 internal regulator disabled note 5: vdd33txrx1 , vdd33txrx2 , vdd33bias , vdd33 , vddio note 6: vdd12tx1 , vdd12tx2 , oscvdd12 , vddcr note 7: current measurements do not include power applied to the magnetics or the optional external leds. note 8: the ethernet component current is independent of the supply rail voltage (2.5v or 3.3v) of the transformer. two copper tp operation is assumed. current is half if one phy is using 100base-fx mode. current is zero if both phys are using 100base-fx mode. note 9: this includes the power dissipated by the transmit ter by way of the current through the transformer. note 10: 3.3*(a) + 1.2*(b) + (2.5)*(c) @ typ note 11: 3.3*(a) + 1.2*(b) + (3.3)*(c) @ typ table 18-4: current consumption and po wer dissipation (regs. disabled) 3.3 v device current (ma) (a) note 5 , note 7 1.2 v device current (ma) (b) note 6 , note 7 tx magnetics current (ma) (c) note 8 device power with 2.5 v magnetics (mw) note 9 , note 10 device power with 3.3 v magnetics (mw) note 9 , note 11 reset ( rst#) typ. 23.6 28.3 0.0 112 112 d0, 100base-tx with traffic typ. 58.7 51.0 82.0 461 526 d0, 100base-txidle typ. 63.4 49.9 82.0 475 540 d0, phy energy detect power down (both phys) typ. 7.9 30.8 0.0 64 63 d0, phy general power down (both phys) typ. 1.5 30.6 0.0 42 42 d1, 100base-txidle typ. 63.4 37.5 82.0 460 525 d1, phy energy detect power down (both phys) typ. 7.8 17.6 0.0 47 47 d1, phy general power down (both phys) typ. 1.5 17.7 0.0 27 27 d2, 100base-txidle typ. 63.4 37.5 82.0 460 525 d2, phy energy detect power down (both phys) typ. 7.8 6.3 0.0 34 34 d2, phy general power down (both phys) typ. 1.5 6.1 0.0 13 13 d3, phy general power down (both phys) typ. 1.5 2.7 0.0 9 9 downloaded from: http:///
lan9252 ds00001909a-page 310 ? 2015 microchip technology inc. 18.4.2 internal regulator enabled note 12: vdd33txrx1 , vdd33txrx2 , vdd33bias , vdd33 , vddio note 13: vdd12tx1 and vdd12tx2 , are driven by the internal regulator vi a the pcb. the current is accounted for via vdd33 . note 14: current measurements do not include power applied to the magnetics or the optional external leds. note 15: the ethernet component current is independent of the supply rail voltage (2.5v or 3.3v) of the transformer. two copper tp operation is assumed. current is half if one phy is using 100base-fx mode. current is zero if both phys are using 100base-fx mode. note 16: this includes the power dissipated by the transmit ter by way of the current through the transformer. note 17: 3.3*(a) + (2.5)*(c) @ typ note 18: 3.3*(a) + (3.3)*(c) @ typ table 18-5: current consumption and power dissipation (regs. enabled) 3.3 v device current (ma) (a) note 12 , note 13 , note 14 tx magnetics current (ma) (c) note 15 device power with 2.5 v magnetics (mw) note 16 , note 17 device power with 3.3 v magnetics (mw) note 16 , note 18 reset ( rst#) typ. 51.2 0.0 169 169 d0, 100base-tx with traffic typ. 112.0 82.0 576 642 d0, 100base-tx idle typ. 113.5 82.0 580 646 d0, phy energy detect power down (both phys) typ. 39.7 0.0 132 132 d0, phy general power down (both phys) typ. 33.0 0.0 109 109 d1, 100base-tx idle typ. 100.5 82.0 537 603 d1, phy energy detect power down (both phys) typ. 26.0 0.0 86 86 d1, phy general power down (both phys) typ. 19.4 0.0 65 65 d2, 100base-tx idle typ. 100.5 82.0 537 603 d2, phy energy detect power down (both phys) typ. 14.8 0.0 49 49 d2, phy general power down (both phys) typ. 7.8 0.0 26 26 d3, phy general power down (both phys) typ. 4.3 0.0 15 15 downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 311 lan9252 18.5 dc specifications table 18-6: non-variable i/o dc electrical characteristics parameter symbol min typ max units notes is type input buffer low input level high input level schmitt trigger hysteresis (v iht - v ilt ) input leakage (v in = vss or vdd33 ) input capacitance pull-up impedance (v in = vss ) pull-down impedance (v in = vdd33 ) v ili v ihi v hys i ih c in r dpu r dpd -0.3 2.0 121 -10 6 52 0.83.6 151 10 3 8.9 79 vv mv a pf k ? k ? note 19 ai type input buffer ( fxsdena/fxsdenb ) low input level high input level v il v ih -0.3 1.2 0.8 vdd33 +0.3 vv ai type input buffer ( rxpa/rxna/rxpb/rxnb) differential input level common mode voltage input capacitance v in-diff v cm c in 0.11.0 vdd33txrx x - 1.3 vdd33txrx x 5 vv pf ai type input buffer ( fxlosen input) state a threshold state b threshold state c threshold v tha v thb v thc -0.3 1.22.3 0.81.7 vdd33 + 0.3 vv v iclk type input buffer ( osci input) low input level high input level input leakage v ili v ihi i ilck -0.3 oscvdd12 -0.35 -10 0.35 3.6 10 vv a note 20 downloaded from: http:///
lan9252 ds00001909a-page 312 ? 2015 microchip technology inc. note 19: this specification applies to all inputs and tri-stated bi-directional pins. internal pull-down and pull-up resis- tors add +/- 50 a per-pin (typical). note 20: osci can optionally be driven from a 25 mhz singled-ended clock oscillator. note 21: lvpecl compatible. note 22: v offset is a function of the external resistor network co nfiguration. the listed value is recommended to pre- vent issues due to crosstalk. ilvpecl input buffer low input level high input level v il - vdd33txrx x v ih - vdd33txrx x vdd33txrx x + 0.3 -1.14 -1.48 0.3 vv note 21 note 21 olvpecl output buffer low output level high output level peak-to-peak differential (sff mode) peak-to-peak differential (sfp mode) common mode voltage offset voltage load capacitance v ol v oh v diff-sff v diff-sfp v cm v offset c load vdd33txrx x - 1.025 1.20.6 1.0 1.6 0.8 vdd33txrx x - 1.3 40 vdd33txrx x - 1.62 2.01.0 10 vv v v v mv pf note 22 table 18-6: non-variable i/o dc electrical characteristics (continued) parameter symbol min typ max units notes downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 313 lan9252 table 18-7: variable i/o dc electrical characteristics parameter symbol min 1.8 v typ 3.3 v typ max units notes vis type input buffer low input level high input level negative-going threshold positive-going threshold schmitt trigger hysteresis (v iht - v ilt ) input leakage (v in = vss or vddio ) input capacitance pull-up impedance (v in = vss ) pull-up current (v in = vss ) pull-down impedance (v in = vdd33 ) pull-down current (v in = vdd33 ) v ili v ihi v ilt v iht v hys i ih c in r dpu i dpu r dpd i dpd -0.3 0.640.81 102 -10 5420 54 19 0.83 0.99 158 6827 68 26 1.411.65 138 8267 85 66 3.6 1.761.90 288 10 2 vv v v mv a pf k ? a k ? a schmitt trigger schmitt trigger note 23 vo8 type buffers low output level high output level v ol v oh vddio - 0.4 0.4 v v i ol = 8 ma i oh = -8 ma vod8 type buffer low output level v ol 0.4 v i ol = 8 ma vo12 type buffers low output level high output level v ol v oh vddio - 0.4 0.4 v v i ol = 12 ma i oh = -12 ma vod12 type buffer low output level v ol 0.4 v i ol = 12 ma vos12 type buffers high output level v oh vddio - 0.4 v i oh = -12 ma vo16 type buffers low output level high output level v ol v oh vddio - 0.4 0.4 v v i ol = 16 ma i oh = -16 ma downloaded from: http:///
lan9252 ds00001909a-page 314 ? 2015 microchip technology inc. note 23: this specification applies to all inputs and tri-stated bi-directional pins. internal pull-down and pull-up resis- tors add 50 a per-pin (typical). note 24: measured at line side of transformer, line replaced by 100 ? (+/- 1%) resistor. note 25: offset from 16 ns pulse width at 50% of pulse peak. note 26: measured differentially. table 18-8: 100base-tx transceiver characteristics parameter symbol min typ max units notes peak differential output voltage high v pph 950 - 1050 mvpk note 24 peak differential output voltage low v ppl -950 - -1050 mvpk note 24 signal amplitude symmetry v ss 98 - 102 % note 24 signal rise and fall time t rf 3.0 - 5.0 ns note 24 rise and fall symmetry t rfs --0 . 5n s note 24 duty cycle distortion d cd 35 50 65 % note 25 overshoot and undershoot v os --5% jitter - - - 1.4 ns note 26 downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 315 lan9252 18.6 ac specifications this section details the various ac timing specifications of the device. note: the i 2 c timing adheres to the nxp i 2 c-bus specification . refer to the nxp i 2 c-bus specification for detailed i 2 c timing information. note: the mii/smi timing adheres to the ieee 802.3 specification . note: the rmii timing adheres to the rmii consortium rmii specification r1.2 . 18.6.1 equivalent test load output timing specifications assume the 25 pf equivalent test load, unless otherwise noted, as illustrated in figure 18-1 . figure 18-1: output equivalent test load 25 pf output downloaded from: http:///
lan9252 ds00001909a-page 316 ? 2015 microchip technology inc. 18.6.2 power sequencing timing these diagrams illustrates the device power sequencing requirements. the vddio , vdd33 , vdd33txrx1 , vdd33txrx2 , vdd33bias and magnetics power supplies must all reach operational levels within the specified time period t pon . when operating with the internal regulators disabled, vddcr , oscvdd12 , vdd12tx1 and vdd12tx2 are also included into this requirement. in addition, once the vddio power supply reaches 1.0 v, it must reach 80% of its operating voltage level (1.44 v when operating at 1.8 v, 2.0 v when operati ng at 2.5 v, 2.64 v when operating at 3. 3 v) within an additional 15ms. this requirement can be safely ignored if using an external reset as shown in section 18.6.3, "reset and configuration strap timing" . device power supplies can turn off in any order provided they all reach 0 volts within the specified time period t poff . figure 18-2: power sequence timing - internal regulators figure 18-3: power sequence timing - external regulators table 18-9: power sequencing timing values symbol description min typ max units t pon power supply turn on time - - 50 ms t poff power supply turn off time - - 500 ms vddio magnetics power t pon t poff vdd33 , vdd33bias , vdd33txrx1 , vdd33txrx2 vddio magnetics power t pon t poff vdd33 , vdd33bias , vdd33txrx1 , vdd33txrx2 vddcr , oscvdd12 , vdd12tx1 , vdd12tx2 downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 317 lan9252 18.6.3 reset and configuration strap timing this diagram illustrates the rst# pin timing requirements and its relation to the configuration strap pins and output drive. assertion of rst# is not a requirement. however, if used, it must be asserted for the minimum period specified. the rst# pin can be asserted at any ti me, but must not be deasserted until t purstd after all external power supplies have reached operational levels. refer to section 6.2, "resets," on page 38 for additional information. note: the clock input must be stable prior to rst# deassertion. note: device configuration straps are latched as a result of rst# assertion. refer to section 6.2.1, "chip-level resets," on page 39 for details. note: configuration strap latching and output drive timings shown assume that the power-on reset has finished first otherwise the timings in section 18.6.4, "power-on and configuration strap timing" apply. figure 18-4: rst# pin configura tion strap latching timing table 18-10: rst# pin configuration strap latching timing values symbol description min typ max units t purstd external power supplies at operational level to rst# deasser- tion 25 ms t rstia rst# input assertion time 200 - - ? s t css configuration strap pins setup to rst# deassertion 200 - - ns t csh configuration strap pins hold after rst# deassertion 10 - - ns t odad output drive after deassertion 3 - - us t css rst# configuration strap pins t rstia t csh output drive t odad ? ? all external power supplies t purstd v opp downloaded from: http:///
lan9252 ds00001909a-page 318 ? 2015 microchip technology inc. 18.6.4 power-on and conf iguration strap timing this diagram illustrates the configurati on strap valid timing requirements in relation to power-on. in order for valid con- figuration strap values to be read at power-on, the following timing requirements must be met. note: configuration straps must only be pulled high or low. configuration straps must not be driven as inputs. device configuration straps are also latched as a result of rst# assertion. refer to section 18.6.3, "r eset and config- uration strap timing" and section 6.2.1, "chip-level resets," on page 39 for additional details. figure 18-5: power-on configura tion strap latching timing table 18-11: power-on configuratio n strap latching timing values symbol description min typ max units t cfg configuration strap valid time - - 15 ms all external power supplies configuration straps t cfg vopp downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 319 lan9252 18.6.5 host bus in terface i/o timing timing specifications for the host bus interface are given in section 9.4.5, "multiplexed addressing mode timing requirements," on page 78 and section 9.5.7, "indexed addressing mode timing requirements," on page 98 . 18.6.6 spi/sqi slave interface i/o timing timing specifications for the spi/sqi slave bus interface are given in section 10.3, "spi/sqi timing requirements," on page 119 . 18.6.7 i 2 c eeprom i/o timing timing specifications for i 2 c eeprom access are given in section 13.1, "i2c interface timing requirements," on page 295 . 18.6.8 ethercat mii port ma nagement access i/o timing timing specifications for the mii port management access are given in section 12.9.7, "exter nal phy timing," on page 206 . 18.6.9 mii i/o timing timing specifications for the mii port interface are given in section 12.9.7, "externa l phy timing," on page 206 . 18.6.10 jtag timing timing specifications for the jtag interface are given in table 17.1.1, jtag timing requirements, on page 306 . downloaded from: http:///
lan9252 ds00001909a-page 320 ? 2015 microchip technology inc. 18.7 clock circuit the device can accept either a 25 mhz crystal or a 25 mhz si ngle-ended clock oscillator (50 ppm) input. if the single- ended clock oscillator method is implemented, osco should be left unconnected and osci should be driven with a clock signal that adheres to the specifications outlined throughout section 18.0, "operational characteristics" . see table 18-12 for the recommended crystal specifications. note 27: the maximum allowable values for frequency tolerance and frequency stability are application dependent. since any particular application must meet the ieee 50 ppm total ppm budge t, the combination of these two values must be approximately 45 ppm (allowing for aging). note 28: frequency deviation over time is also referred to as aging. note 29: the total deviation for 100base-tx is 50 ppm. note 30: the maximum allowable values for frequency tolerance and frequency stability are application dependent. since any particular application mu st meet the ethercat 25 ppm total ppm budget, the combination of these two values must be approximately 15 ppm (allowing for aging). table 18-12: crystal specifications parameter symbol min nom max units notes crystal cut at, typ crystal oscillation mode fundamental mode crystal calibration mode parallel resonant mode frequency f fund - 25.000 - mhz 802.3 frequency tolerance at 25 o c f tol - - 40 ppm note 27 802.3 frequency stability over te m p f temp - - 40 ppm note 27 802.3 frequency deviation over time f age - 3 to 5 - ppm note 28 802.3 total allowable ppm bud- get - - 50 ppm note 29 ethercat frequency tolerance at 25 o c f tol - - 15 ppm note 30 ethercat frequency stability over temp f temp - - 15 ppm note 30 ethercat frequency deviation over time f age - 3 to 5 - ppm note 28 ethercat total allowable ppm budget - - 25 ppm note 31 shunt capacitance c o --7p f load capacitance c l - - 18 pf drive level p w 300 note 32 -- w equivalent series resistance r 1 --1 0 0 ? operating temperature range note 33 - note 34 o c osci pin capacitance - 3 typ - pf note 35 osco pin capacitance - 3 typ - pf note 35 downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 321 lan9252 note 31: the total deviation for ethercat is 25 ppm. note 32: the minimum drive level requirement p w is reduced to 100 uw with the addition of a 500 ? series resistor, if c o ? 5pf, c l ? 12 pf and r1 ? 80 ? note 33: 0 c for commercial version, -40 c for industrial and extended industrial versions note 34: +70 c for commercial version, +85 c for industrial version, +105 c for extended industrial version note 35: this number includes the pad, the bond wire and the lead frame. pcb capacitance is not included in this value. the osci pin, osco pin and pcb capacitance values are required to accurately calculate the value of the two external load capacitors. the total load capacitance must be equivalent to what the crystal expects to see in the circuit so that the crystal oscillator will operate at 25.000 mhz. downloaded from: http:///
lan9252 ds00001909a-page 322 ? 2015 microchip technology inc. 19.0 package outlines 19.1 64-qfn figure 19-1: 64-qfn package downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 323 lan9252 figure 19-2: 64-qfn package dimensions downloaded from: http:///
lan9252 ds00001909a-page 324 ? 2015 microchip technology inc. 19.2 64-tqfp-ep figure 19-3: 64-tqfp-ep package downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 325 lan9252 20.0 revision history table 20-1: revision history revision level section/figure/entry correction ds00001909a (04-08-15) initial release downloaded from: http:///
lan9252 ds00001909a-page 326 ? 2015 microchip technology inc. the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site con- tains the following information: product support C data sheets and errata, application notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software general technical support C frequently asked questions (faq), te chnical support requests, online discussion groups, microchip consultant program member listing business of microchip C product selector and ordering guides, latest microchip press releases, listing of semi- nars and events, listings of microchip sales offi ces, distributors and factory representatives customer change notification service microchips customer notification service helps keep custom ers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisi ons or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under support, click on customer change notifi- cation and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this docu- ment. technical support is available through the web site at: http://microchip.com/support downloaded from: http:///
? 2015 microchip technology inc. ds00001909a-page 327 lan9252 product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . device: lan9252 tape and reel option: blank = standard packaging (tray) t = tape and reel ( note 1 ) temperature range: blank = 0 ? c to +70 ? c (commercial) i= - 4 0 ? c to +85 ? c (industrial) v= - 4 0 ? c to +105 ? c (extended industrial) ( note 2 ) package: ml = 64-pin qfn pt = 64-pin tqfp-ep examples: a) lan9252/ml standard packaging (tray), commercial temperature, 64-pin qfn b) lan9252ti/pt tape and reel industrial temperature, 64-pin tqfp-ep note 1: tape and reel identifier only appears in the catalog part number description. this identifier is used for ordering purposes and is not printed on the device package. check with your microchip sales office for package availability with the tape and reel option. 2: extended industrial temp. support (105 o c) in the 64-qfn only part no. device tape and reel option / temperature range xx [x] [x] package downloaded from: http:///
lan9252 ds00001909a-page 328 ? 2015 microchip technology inc. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer can guarantee the securi ty of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchips code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with y our specifications. microchip make s no representations or warranties of any kind whether ex press or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fi tness for purpose . microchip disclaims all liability arising fr om this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, i ndemnify and hold harmless microchip from any and all dama ges, claims, suits, or expenses resulting from such use. no licenses are conveyed, implic- itly or otherwise, under any micr ochip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. the embedded control solutions company and mtouch are registered tr ademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kl eernet, kleernet logo, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem .net, pickit, pictail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbcheck, varisense, view span, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchi p technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademarks of microc hip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are pr operty of their respective companies. ? 2015, microchip technology incorporated, pr inted in the u.s.a., all rights reserved. isbn:9781632771957 microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the companys quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchips quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == downloaded from: http:///
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